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Formal system-level design space exploration

Published: 01 February 2013 Publication History

Abstract

DIPLODOCUS is a UML profile intended for the modeling and the formal verification of real-time and embedded applications commonly executed on complex Systems-on-Chip. DIPLODOCUS implements the Y-chart approach, that is, application and HW architecture e.g., CPUs, bus, memories are first described independently and are subsequently related to each other in a mapping stage. Abstract tasks and communication primitives are therefore mapped onto platform elements like buses and CPUs. DIPLODOCUS endows all models with a formal semantics, thereby paving the way for formal proofs both before and after mapping. More concretely, application, architecture, and mapping models can be edited in TTool - an open-source toolkit - using UML diagrams. Then, pre-mapping or post-mapping UML models may be automatically transformed into a LOTOS-based representation. This specification is in turn amenable to model-checking techniques to evaluate properties of the system, for example, safety, schedulability, and performance properties. A smart card system serves as case study to illustrate the formal verification capabilities of DIPLODOCUS. Copyright © 2012 John Wiley & Sons, Ltd.

References

[1]
Kienhuis B, Deprettere EF, Wolf Pvd, Vissers KA. A methodology to design programmable embedded systems - the Y-chart approach. In Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS. Springer-Verlag: London, UK, 2002; pp.18-37.
[2]
Apvrille L etal. A UML-based environment for system design space exploration. 13th IEEE International Conference on Electronics, Circuits and Systems ICECS'2006, Nice, France, 2006.
[3]
Knorreck D, Apvrille L, Pacalet R. Fast simulation techniques for design space exploration. In Objects, Components, Models and Patterns, Lecture Notes in Business Information Processing, Vol.Volume 33. Springer Berlin Heidelberg, 2009; pp.308-327.
[4]
Apvrille L. TTool for DIPLODOCUS: an environment for design space exploration. 8th Annual International Conference on New Technologies of Distributed Systems NOTERE'2008, Lyon, France, 2008.
[5]
TTool. http://labsoc.comelec.enst.fr/turtle/ttool.html.
[6]
ISO-LOTOS. A formal description technique based on the temporal ordering of observational behaviour. Draft International Standard 8807, International Organization for Standardization - Information Processing Systems - Open Systems Interconnection, Geneva, 1987.
[7]
Muhammad W etal. Abstract application modeling for system design space exploration. Euromicro Conference on Digital System Design DSD'06, Dubrovnik, Croatia, 2006.
[8]
Balarin F etal. Hardware-Software Co-design of Embedded Systems, the POLIS Approach, 5thed. Kluwer Academic Publishers: Netherlands, 2003.
[9]
Assayad I, Yovine S. A framework for modelling and performance analysis of multiprocessor embedded systems: models and benefits. Proceedings of the 8th Conference on Nouvelles Technologies de la Distribution NOTERE'2007, Marrakech, Morocco, 2007.
[10]
Avnit K, Sowmya A. A formal approach to design space exploration of protocol converters. Design, Automation and Test in Europe Conference and Exhibition, 2009. DATE'09, Nice, France, 2009; pp.129-134.
[11]
Marculescu R, Ogras UY, Zamora NH. Computation and communication refinement for multiprocessor SoC design: a system-level perspective. ACM Transactions on Design Automation of Electronic Systems 2006; Volume 11 Issue 3: pp.564-592.
[12]
Hendriks M, Verhoef M. Timed automata based analysis of embedded system architectures. Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International, Rhodes, Greece, 2006; pp.179-179.
[13]
Watanabe Y. Metropolis: an integrated environment for electronic system design, Cadence Berkeley Labs, 2001.
[14]
Wolf PVD etal. A methodology for architecture exploration of heterogeneous signal processing systems. 1999 IEEE Workshop on Signal Processing Systems SiPS99, Taipei, Taiwan, 1999.
[15]
Chatelain A etal. High-level architectural co-simulation using Esterel and C. Proceedings of the Ninth International Symposium on Hardware/Software Codesign, Copenhagen, Denmark, 2001.
[16]
Schattkowsky T etal. A model-based approach for executable specifications on reconfigurable hardware. Design, Automation and Test in Europe Conference and Exhibition, 2005. DATE'05, Munich, Germany, 2005; pp.692-697.
[17]
Kukkala P etal. Performance modeling and reporting for the UML 2.0 design of embedded systems. International Symposium on System-on-Chip, 2005. Proceedings, Tampere, Finland, 2005; pp.50-53.
[18]
Vidal J, deLamotte F, Gogniat G, Soulard P, Diguet JP. A co-design approach for embedded system modeling and code generation with UML and MARTE. Design, Automation and Test in Europe Conference and Exhibition, 2009. DATE'09, Nice, France, 2009; pp.226-231.
[19]
Woodside M, Petriu DC, Petriu DB, Shen H, Israr T, Merseguer J. Performance by unified model analysis PUMA. WOSP '05: Proceedings of the 5th International Workshop on Software and Performance, ACM, New York, NY, USA, 2005; pp.1-12.
[20]
Viehl A, Schonwald T, Bringmann O, Rosenstiel W. Formal performance analysis and simulation of UML/sysML models for ESL design. Design, Automation and Test in Europe Conference and Exhibition, 2006. DATE'06 2006; Volume 1: pp.1-6.
[21]
Ristau B, Limberg T, Fettweis G. A mapping framework for guided design space exploration of heterogeneous MP-SoCs. Design, Automation and Test in Europe Conference and Exhibition, 2008. DATE'08, Munich, Germany, 2008; pp.780-783.
[22]
Hamann A, Jersak M, Richter K, Ernst R. A framework for modular analysis and exploration of heterogeneous embedded systems. Real-Time Systems 2006; Volume 33 Issue 1-3: pp.101-137.
[23]
Henia R, Hamann A, Jersak M, Racu R, Richter K, Ernst R. System level performance analysis - the SymTA/S approach. Computers and Digital Techniques, IEE Proceedings - 2005; Volume 152 Issue 2: pp.148-166.
[24]
Wodey P, Camarroque G, Baray F, Hersemeule R, Cousin JP. LOTOS code generation for model checking of STBus based SoC: the STBus interconnection. This paper appears in: Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings. First ACM and IEEE International Conference on, Mont St. Michel, France, 2003; pp.204-213.
[25]
OMG. UML 2.0 Superstructure Specification, Geneva, 2003. http://www.omg.org/docs/ptc/03-08-02.pdf.
[26]
Garavel H, Lang F, Mateescu R, Serwe W. CADP 2006: a toolbox for the construction and analysis of distributed processes. In Computer Aided Verification CAV'2007, Vol.Volume 4590: Berlin, Germany, 2007; pp.158-163.
[27]
Jaber C, Kanstein A, Apvrille L, Baghdadi A, Moenner PL, Pacalet R. High-level system modeling for rapid HW/SW architecture exploration. Proc. of the 20th IEEE/IFIP International Symposium on Rapid System Prototyping RSP'2009, Paris, France, 2009.
[28]
Apvrille L etal. TURTLE: a real-time UML profile supported by a formal validation toolkit. In IEEE Transactions on Software Engineering, Vol. Volume 30, 2004; pp.473-487.
[29]
Ahumada S etal. Specifying Fractal and GCM components with UML. XXVI International Conference of the Chilean Computer Science Society SCCC'07, Iquique, Chile, 2007.
[30]
Knorreck D, Apvrille L, Saqui-Sannes Pd. TEPE: a SysML language for time-constrained property modeling and formal verification. <bookSeriesTitle>Proceedings of the Third IEEE International Workshop UML and Formal Methods - ULM&FM'2010</bookSeriesTitle>, 2010.
[31]
Knorreck D, Apvrille L, Pacalet R. An interactive system level simulation environment for Systems on Chip. ERTSS - Embedded Real Time Software and Systems, Toulouse, France, 2010.
[32]
Iso 7816 smart card standard:. http://www.cardwerk.com/smartcards/smartcard_standard_ISO7816.aspx.
[33]
Idrees MS, Roudier Y, Apvrille L. A framework towards the efficient identification and modelling of security requirements. Fifth Conference on the Security of Network Architecture and Information Systems SAR-SSI 2010, Menton, France, 2010.

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  • (2024)AI-Driven Consistency of SysML DiagramsProceedings of the ACM/IEEE 27th International Conference on Model Driven Engineering Languages and Systems10.1145/3640310.3674079(149-159)Online publication date: 22-Sep-2024

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Published In

cover image Concurrency and Computation: Practice & Experience
Concurrency and Computation: Practice & Experience  Volume 25, Issue 2
February 2013
129 pages
ISSN:1532-0626
EISSN:1532-0634
Issue’s Table of Contents

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John Wiley and Sons Ltd.

United Kingdom

Publication History

Published: 01 February 2013

Author Tags

  1. TTool
  2. UML
  3. design space exploration
  4. formal specification
  5. model checking
  6. systems-on-chip

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  • (2024)AI-Driven Consistency of SysML DiagramsProceedings of the ACM/IEEE 27th International Conference on Model Driven Engineering Languages and Systems10.1145/3640310.3674079(149-159)Online publication date: 22-Sep-2024

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