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A New Bit-Serial Systolic Multiplier Over GF(2/sup m/)

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B. B. ZhouAuthors Info & Claims

IEEE Transactions on Computers, Volume 37, Issue 6

Pages 749 - 751

https://doi.org/10.1109/12.2216

Published: 01 June 1988 Publication History

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Abstract

A bit-serial systolic array has been developed to computer multiplications over GF(2/sup m/). In contrast to a previously designed systolic multiplier, this algorithm allows the input elements to center a linear systolic array in the same order, and the system only requires one control signal.

References

[1]

{1} H. T. Kung, "Why systolic architectures?," IEEE Computer, vol. 15, pp. 37-46, Jan. 1982.

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[2]

{2} F. J. Macwilliams and N. J. Sloane, The Theory of Error-Correcting Codes. Amsterdam: North-Holland, 1977.

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[3]

{3} C. A. Mead and L. A. Conway, Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980.

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[4]

{4} C. C. Wang, T. K. Truong, H. M. Shao, L. J. Deutsch, J. K. Omura, and I. S. Reed, "VLSI architectures for computing multiplications and inverses in GF(2<sup>m</sup>)," IEEE Trans. Comput., vol. C-34, Aug. 1985.

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Google Scholar

[5]

{5} C.-S. Yeh, I. S. Reed, and T. K. Truong, "Systolic multipliers for finite field GF(2<sup>m</sup>)," IEEE Trans. Comput., vol. C-33, pp. 357-360, Apr. 1984.

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Cited By

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Lee C(2008)Low-complexity bit-parallel systolic multipliers over GF(2)Integration, the VLSI Journal10.1016/j.vlsi.2007.05.00141:1(106-112)Online publication date: 1-Jan-2008
https://dl.acm.org/doi/10.1016/j.vlsi.2007.05.001
Kwon SKim CHong C(2005)Unidirectional two dimensional systolic array for multiplication in GF(2) using LSB first algorithmProceedings of the 6th international conference on Fuzzy Logic and Applications10.1007/11676935_52(420-426)Online publication date: 15-Sep-2005
https://dl.acm.org/doi/10.1007/11676935_52
Kwon SKim CHong C(2005)Compact linear systolic arrays for multiplication using a trinomial basis in GF(2) for high speed cryptographic processorsProceedings of the 2005 international conference on Computational Science and its Applications - Volume Part I10.1007/11424758_53(508-518)Online publication date: 9-May-2005
https://dl.acm.org/doi/10.1007/11424758_53
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Index Terms

A New Bit-Serial Systolic Multiplier Over GF(2/sup m/)
1. Hardware
  1. Very large scale integration design
    1. VLSI system specification and constraints
2. Mathematics of computing
  1. Mathematical analysis
    1. Numerical analysis
      1. Arbitrary-precision arithmetic
      2. Interval arithmetic

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cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 37, Issue 6

June 1988

136 pages

ISSN:0018-9340

Editor:
Bruce D. Shriver

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IEEE Computer Society

United States

Publication History

Published: 01 June 1988

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Lee C(2008)Low-complexity bit-parallel systolic multipliers over GF(2)Integration, the VLSI Journal10.1016/j.vlsi.2007.05.00141:1(106-112)Online publication date: 1-Jan-2008
https://dl.acm.org/doi/10.1016/j.vlsi.2007.05.001
Kwon SKim CHong C(2005)Unidirectional two dimensional systolic array for multiplication in GF(2) using LSB first algorithmProceedings of the 6th international conference on Fuzzy Logic and Applications10.1007/11676935_52(420-426)Online publication date: 15-Sep-2005
https://dl.acm.org/doi/10.1007/11676935_52
Kwon SKim CHong C(2005)Compact linear systolic arrays for multiplication using a trinomial basis in GF(2) for high speed cryptographic processorsProceedings of the 2005 international conference on Computational Science and its Applications - Volume Part I10.1007/11424758_53(508-518)Online publication date: 9-May-2005
https://dl.acm.org/doi/10.1007/11424758_53
Mekhallalati MAshur AIbrahim M(1997)Novel Radix Finite Field Multiplier for GF(2m)Journal of VLSI Signal Processing Systems10.5555/257692.281304015:3(233-245)Online publication date: 1-Mar-1997
https://dl.acm.org/doi/10.5555/257692.2813040
Mekhallalati MAshur AIbrahim M(1997)Novel Radix Finite Field Multiplier for GF(2 ^m )Journal of VLSI Signal Processing Systems10.5555/257692.25770215:3(233-245)Online publication date: 1-Mar-1997
https://dl.acm.org/doi/10.5555/257692.257702
Wu CChang M(1995)Bit-level systolic arrays for finite-field multiplicationsJournal of VLSI Signal Processing Systems10.1007/BF0240702810:1(85-92)Online publication date: 1-Jun-1995
https://dl.acm.org/doi/10.1007/BF02407028

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Bit-Serial Systolic Divider and Multiplier for Finite Fields GF(2/sup m/)

A Systolic Power-Sum Circuit for GF(2/sup m/)

Super Digit-Serial Systolic Multiplier over GF(2^m)

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