research-article

Functional Test Generation Based on Unate Function Theory

Authors:

Vijay Pitchumani,

Satish S. SomanAuthors Info & Claims

IEEE Transactions on Computers, Volume 37, Issue 6

Pages 756 - 760

https://doi.org/10.1109/12.2218

Published: 01 June 1988 Publication History

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Abstract

The generation of a universal test set (UTS) for unate functions is used as a starting point. This test set is complete and minimal for the set of all unateness-preserving faults. However, for functions that are not unate in any variable, the UTS generated by this algorithm is the exhaustive set. An algorithm is presented that computes a good functional test set (GFTS) of reasonable size even for such functions. The algorithm does this by breaking up functions into more unate components, recursively computing GFTS for them, and combining the test sets in an appropriate way. The GFTS generated by the algorithm is compared to random test sets of the same size for gate-level fault coverage in typical implementations.

References

[1]

{1} R. Betancourt, "Derivation of minimum test sets for unate logical circuits," IEEE Trans. Comput., vol. C-20, pp. 1264-1269, Nov. 1971.

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[2]

{2} S. B. Akers, "Universal test sets for logic networks," in Proc. 13th Annu. Switching Automata Theory Symp., Oct. 1972, pp. 177-184.

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[3]

{3} S. M. Reddy, "Complete test sets for logic functions," IEEE Trans. Comput., vol. C-22, pp. 1016-1020, Nov. 1973.

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{4} R. K. Brayton, G. D. Hachtel, C. T. McMullen, and A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis. Boston, MA: Kluwer Academic, 1984.

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[5]

{5} R. McNaughton, "Unate truth functions," IRE Trans. Electron. Comput., vol. EC-10, pp. 1-6, Mar. 1961.

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Index Terms

Functional Test Generation Based on Unate Function Theory
1. Hardware
  1. Hardware test
    1. Test-pattern generation and fault simulation

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cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 37, Issue 6

June 1988

136 pages

ISSN:0018-9340

Editor:
Bruce D. Shriver

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IEEE Computer Society

United States

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Published: 01 June 1988

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Functional test generation for delay faults in combinational circuits

On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits

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