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Principles of Asynchronous Circuit Design: A Systems PerspectiveOctober 2010
- Authors:
- Jens Spars,
- Steve Furber
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Abstract
Principles of Asynchronous Circuit Design - A Systems Perspective addresses the need for an introductory text on asynchronous circuit design. Part I is an 8-chapter tutorial which addresses the most important issues for the beginner, including how to think about asynchronous systems. Part II is a 4-chapter introduction to Balsa, a freely-available synthesis system for asynchronous circuits which will enable the reader to get hands-on experience of designing high-level asynchronous systems. Part III offers a number of examples of state-of-the-art asynchronous systems to illustrate what can be built using asynchronous techniques. The examples range from a complete commercial smart card chip to complex microprocessors. The objective in writing this book has been to enable industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task.
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- El-Hadbi A, Cherkaoui A, Elissati O, Simatic J and Fesquet L (2018). An accurate time-to-digital converter based on a self-timed ring oscillator for on-the-fly time measurement, Analog Integrated Circuits and Signal Processing, 97:3, (471-481), Online publication date: 1-Dec-2018.
- Raji M and Ghavami B (2018). Redressing fork constraints in nanoscale quasi-delay-insensitive asynchronous pipelines, The Journal of Supercomputing, 74:8, (3820-3840), Online publication date: 1-Aug-2018.
- Kudo T and Saito H Comparison of Pipelined Asynchronous Circuits Designed for FPGA Proceedings of the 3rd International Conference on Applications in Information Technology, (69-74)
- Guazzelli R, Moreira M, Neto W and Calazans N Sleep convention logic isochronic fork Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, (103-109)
- Sokolov D, Dubikhin V, Khomenko V, Lloyd D, Mokhov A and Yakovlev A Benefits of asynchronous control for analog electronics Proceedings of the Conference on Design, Automation & Test in Europe, (1755-1760)
- Shih C, Shih C and Jiang J Closing the Accuracy Gap of Static Performance Analysis of Asynchronous Circuits Proceedings of the 54th Annual Design Automation Conference 2017, (1-6)
- Huang K, Shen T and Li C Test Methodology for Dual-rail Asynchronous Circuits Proceedings of the 54th Annual Design Automation Conference 2017, (1-6)
- Balasubramanian P (2016). Comments on "Dual-rail asynchronous logic multi-level implementation", Integration, the VLSI Journal, 52:C, (34-40), Online publication date: 1-Jan-2016.
- Wu G and Chu C Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuits Proceedings of the 2016 Conference on Design, Automation & Test in Europe, (1042-1047)
- Compositional design of asynchronous circuits from behavioural concepts Proceedings of the 2015 ACM/IEEE International Conference on Formal Methods and Models for Codesign, (118-127)
- Constantin J, Wang L, Karakonstantis G, Chattopadhyay A and Burg A Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, (381-386)
- Huang B, Lai Y and Jiang J Asynchronous QDI Circuit Synthesis from Signal Transition Protocols Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, (434-441)
- Wang Z, He X and Sechen C (2015). A New Approach for Gate-Level Delay-Insensitive Asynchronous Logic, Circuits, Systems, and Signal Processing, 34:5, (1431-1459), Online publication date: 1-May-2015.
- Yang J (2015). A simple fault tolerant control for input/output asynchronous sequential machines, Automatica (Journal of IFAC), 52:C, (76-82), Online publication date: 1-Feb-2015.
- De V, Kahng A, Karnik T, Liu B, Maleki M and Wang L (2015). Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design, ACM Journal on Emerging Technologies in Computing Systems, 12:3, (1-19), Online publication date: 21-Sep-2015.
- Song W, Zhang G and Garside J On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip Proceedings of the 24th edition of the great lakes symposium on VLSI, (211-216)
- Ho K and Chang Y A New Asynchronous Pipeline Template for Power and Performance Optimization Proceedings of the 51st Annual Design Automation Conference, (1-6)
- Chuang C, Lai Y and Jiang J Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits Proceedings of the 51st Annual Design Automation Conference, (1-6)
- Shang D, Zhang X, Xia F and Yakovlev A Asynchronous design for new on-chip wide dynamic range power electronics Proceedings of the conference on Design, Automation & Test in Europe, (1-6)
- Wang Z, He X and Sechen C TonyChopper Proceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design, (446-453)
- Zhang G, Song W, Garside J, Navaridas J and Wang Z (2014). Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes, Microprocessors & Microsystems, 38:8, (826-842), Online publication date: 1-Nov-2014.
- Peper F, Lee J, Carmona J, Cortadella J and Morita K (2013). Brownian Circuits, ACM Journal on Emerging Technologies in Computing Systems, 9:1, (1-24), Online publication date: 1-Feb-2013.
- Ghavami B, Raji M, Pedram H and Tahoori M (2013). Design and Analysis of a Robust Carbon Nanotube-Based Asynchronous Primitive Circuit, ACM Journal on Emerging Technologies in Computing Systems, 9:1, (1-27), Online publication date: 1-Feb-2013.
- Huang Y, Ienne P, Temam O, Chen Y and Wu C Elastic CGRAs Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays, (171-180)
- Yakovlev A, Vivet P and Renaudin M Advances in asynchronous logic Proceedings of the Conference on Design, Automation and Test in Europe, (1715-1724)
- Fernandes J, Koutny M, Pietkiewicz-Koutny M, Sokolov D and Yakovlev A Step persistence in the design of GALS systems Proceedings of the 34th international conference on Application and Theory of Petri Nets and Concurrency, (190-209)
- Liu B, Chen X and Teshome F (2012). Resilient and adaptive performance logic, ACM Journal on Emerging Technologies in Computing Systems, 8:3, (1-16), Online publication date: 1-Aug-2012.
- Song W, Edwards D, Garside J and Bainbridge W Area efficient asynchronous SDM routers using 2-stage clos switches Proceedings of the Conference on Design, Automation and Test in Europe, (1495-1500)
- Mokhov A, Sokolov D, Rykunov M and Yakovlev A Formal modelling and transformations of processor instruction sets Proceedings of the Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign, (51-60)
- Zamani M and Tahoori M Variation-immune quasi delay-insensitive implementation on nano-crossbar arrays Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI, (181-186)
- Boddapati H, Naregalkar A and Raju B Novel asynchronous adders Proceedings of the International Conference & Workshop on Emerging Trends in Technology, (1055-1058)
- Rosa T, Guindani G, Cardoso D, Calazans N and Moraes F A self-adaptable distributed DFS scheme for NoC-based MPSoCs Proceedings of the 24th symposium on Integrated circuits and systems design, (203-208)
- Vacca M, Graziano M and Zamboni M (2011). Asynchronous Solutions for Nanomagnetic Logic Circuits, ACM Journal on Emerging Technologies in Computing Systems (JETC), 7:4, (1-18), Online publication date: 1-Dec-2011.
- Stuart M, Stensgaard M and Sparsø J (2011). The ReNoC Reconfigurable Network-on-Chip, ACM Transactions on Embedded Computing Systems (TECS), 10:4, (1-26), Online publication date: 1-Nov-2011.
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- Van Leuken R, Van Leeuwen T and Arriens H High level synthesis of asynchronous circuits from data flow graphs Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation, (317-330)
- Tran A, Truong D and Baas B (2019). A reconfigurable source-synchronous on-chip network for GALS many-core platforms, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29:6, (897-910), Online publication date: 1-Jun-2010.
- Wenck J, Collier J, Siebert J and Amirtharajah R (2008). Scaling self-timed systems powered by mechanical vibration energy harvesting, ACM Journal on Emerging Technologies in Computing Systems (JETC), 6:2, (1-24), Online publication date: 1-Jun-2010.
- Pragasam D and Sam D Asynchronous computing in low power based sense amplifier pass transistor logic Proceedings of the 12th international conference on Networking, VLSI and signal processing, (193-196)
- Chakraborty R and Bhunia S (2009). A study of asynchronous design methodology for robust CMOS-nano hybrid system design, ACM Journal on Emerging Technologies in Computing Systems (JETC), 5:3, (1-22), Online publication date: 1-Aug-2009.
- Gagné R, Belzile J and Thibeault C (2009). From synchronous to GALS, Microelectronics Journal, 40:11, (1657-1666), Online publication date: 1-Nov-2009.
- Liu T, Alarcón L, Pierson M and Rabaey J (2018). Asynchronous computing in sense amplifier-based pass transistor logic, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17:7, (883-892), Online publication date: 1-Jul-2009.
- Nielsen S, Sparsø J and Madsen J (2019). Behavioral synthesis of asynchronous circuits using syntax directed translation as backend, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17:2, (248-261), Online publication date: 1-Feb-2009.
- Ghavami B, Pedram H and Najibi M (2009). An EDA tool for implementation of low power and secure crypto-chips, Computers and Electrical Engineering, 35:2, (244-257), Online publication date: 1-Mar-2009.
- Oh M and Kim S (2018). Low Static Powered Asynchronous Data Transfer for GALS System, IEICE - Transactions on Information and Systems, E91-D:4, (1189-1192), Online publication date: 1-Apr-2008.
- Mokhov A and Yakovlev A Conditional partial order graphs and dynamically reconfigurable control synthesis Proceedings of the conference on Design, automation and test in Europe, (1142-1147)
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- Tran X, Thonnart Y, Durupt J, Beroulle V and Robach C A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, (149-158)
- Sheibanyrad A and Greiner A (2008). Two efficient synchronous ↔ asynchronous converters well-suited for networks-on-chip in GALS architectures, Integration, the VLSI Journal, 41:1, (17-26), Online publication date: 1-Jan-2008.
- Mahram A, Najibi M and Pedram H An asynchronous fpga logic cell implementation Proceedings of the 17th ACM Great Lakes symposium on VLSI, (176-179)
- Najibi M, Saleh K and Pedram H Using standard asic back-end for qdi asynchronous circuits Proceedings of the 17th ACM Great Lakes symposium on VLSI, (299-304)
- Kawokgy M and Salama C A low-power CSCD asynchronous viterbi decoder for wireless applications Proceedings of the 2007 international symposium on Low power electronics and design, (363-366)
- Taubin A, Cortadella J, Lavagno L, Kondratyev A and Peeters A (2018). Design automation of real-life asynchronous devices and systems, Foundations and Trends in Electronic Design Automation, 2:1, (1-133), Online publication date: 1-Jan-2007.
- Bjerregaard T, Stensgaard M and Sparsø J A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method Proceedings of the conference on Design, automation and test in Europe, (648-653)
- Wielage P, Marinissen E, Altheimer M and Wouters C Design and DfT of a high-speed area-efficient embedded asynchronous FIFO Proceedings of the conference on Design, automation and test in Europe, (853-858)
- Koch-Hofer C, Renaudin M, Thonnart Y and Vivet P ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC Proceedings of the First International Symposium on Networks-on-Chip, (295-306)
- Shang D, Yakovlev A, Koelmans A, Sokolov D and Bystrov A (2019). Registers for phase difference based logic, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15:6, (720-724), Online publication date: 1-Jun-2007.
- Poliakov I, Sokolov D and Mokhov A Workcraft Proceedings of the 28th international conference on Applications and theory of Petri nets and other models of concurrency, (505-514)
- Liu Y, Chen P, Xie G, Liu G and Li Z Evaluating a low-power dual-core architecture Proceedings of the 7th international conference on Advanced parallel processing technologies, (80-89)
- Shang D, Shin C, Wang P, Xia F, Koelmans A, Oh M, Kim S and Yakovlev A Asynchronous functional coupling for low power sensor network processors Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation, (53-63)
- Liu Y, Chen P, Wang W and Li Z The design and implementation of a power efficient embedded SRAM Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation, (86-96)
- Ghavami B and Pedram H An automatic design flow for implementation of side channel attacks resistant crypto-chips Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation, (330-339)
- Ghavami B, Niknahad M, Najibi M and Pedram H A fast and accurate power estimation methodology for QDI asynchronous circuits Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation, (463-473)
- Mocho R, Sartori G, Ribas R and Reis A Asynchronous circuit design on reconfigurable devices Proceedings of the 19th annual symposium on Integrated circuits and systems design, (20-25)
- Kulikowski K, Smirnov A and Taubin A Automated design of cryptographic devices resistant to multiple side-channel attacks Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems, (399-413)
- Monnet Y, Renaudin M and Leveugle R (2019). Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic, IEEE Transactions on Computers, 55:9, (1104-1115), Online publication date: 1-Sep-2006.
- Oikonomakos P, Fournier J and Moore S Implementing cryptography on TFT technology for secure display applications Proceedings of the 7th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications, (32-47)
- Liu Y, Furber S and Li Z The design of a dataflow coprocessor for low power embedded hierarchical processing Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation, (425-438)
- Yahya E and Renaudin M QDI latches characteristics and asynchronous linear-pipeline performance analysis Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation, (583-592)
- Razafindraibe A, Robert M and Maurine P Formal evaluation of the robustness of dual-rail logic against DPA attacks Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation, (634-644)
- Bjerregaard T and Mahadevan S (2006). A survey of research and practices of Network-on-chip, ACM Computing Surveys (CSUR), 38:1, (1-es), Online publication date: 29-Jun-2006.
- Sokolov D, Murphy J, Bystrov A and Yakovlev A (2005). Design and Analysis of Dual-Rail Circuits for Security Applications, IEEE Transactions on Computers, 54:4, (449-460), Online publication date: 1-Apr-2005.
- Bjerregaard T and Sparso J A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip Proceedings of the conference on Design, Automation and Test in Europe - Volume 2, (1226-1231)
- Liu Y and Furber S The design of an asynchronous carry-lookahead adder based on data characteristics Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation, (647-656)
- Razafindraibe A, Robert M, Renaudin M and Maurine P A method to design compact DUAL-RAIL asynchronous primitives Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation, (571-580)
- Kawokgy M and Salama C Low-power asynchronous viterbi decoder for wireless applications Proceedings of the 2004 international symposium on Low power electronics and design, (286-289)
- Liu Y and Furber S The design of a low power asynchronous multiplier Proceedings of the 2004 international symposium on Low power electronics and design, (301-306)
- Peeters A Implementation of handshake components Proceedings of the 2004 international conference on Communicating Sequential Processes: the First 25 Years, (98-132)
- Te Beest F, Peeters A, Van Berkel K and Kerkhoff H (2019). Synchronous Full-Scan for Asynchronous Handshake Circuits, Journal of Electronic Testing: Theory and Applications, 19:4, (397-406), Online publication date: 1-Aug-2003.
- Yang J and Brunvand E Using dynamic domino circuits in self-timed systems Proceedings of the 13th ACM Great Lakes symposium on VLSI, (253-256)
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