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View all- Li XJain AMaskell DFahmy S(2018)A time-multiplexed FPGA overlay with linear interconnect2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2018.8342171(1075-1080)Online publication date: Mar-2018
- Monson JHutchings B(2018)Enhancing debug observability for HLS-based FPGA circuits through source-to-source compilationJournal of Parallel and Distributed Computing10.1016/j.jpdc.2018.02.012117:C(148-160)Online publication date: 1-Jul-2018
- Arato PSuba G(2014)A data flow graph generation method starting from c description by handling loop nest hierarchy2014 IEEE 9th IEEE International Symposium on Applied Computational Intelligence and Informatics (SACI)10.1109/SACI.2014.6840074(269-274)Online publication date: May-2014