research-article

Hardware design space exploration using HercuLeS HLS

Authors:

Nikolaos Kavvadias and

Kostas MasselosAuthors Info & Claims

PCI '13: Proceedings of the 17th Panhellenic Conference on Informatics

September 2013

Pages 195 - 202

https://doi.org/10.1145/2491845.2491865

Published: 19 September 2013 Publication History

Abstract

HercuLeS is an extensible high-level synthesis (HLS) environment. It removes significant human effort by automatically mapping algorithms to hardware, providing a valuable design assist to software-oriented developers. To enable accessibility and easiness of hardware design space exploration (DSE), HercuLeS overcomes limitations of known work: non-standard source languages, insufficient representations, maintenance difficulties, necessity of code templates, lack of usage paradigms and vendor-dependence. Specific aspects that are highlighted in this manuscript are: a) the in-nerworkings of the HercuLeS hardware compilation engine, b) manipulation of SSA (Static Single Assignment) form, c) automatic third-party IP integration, d) backend C code generation for compiled simulation, and e) an exemplary case of DSE. HercuLeS enables efficient hardware generation that can closely match the quality of results of a manually-developed implementation with much reduced human effort and time requirements.

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Cited By

Li XJain AMaskell DFahmy S(2018)A time-multiplexed FPGA overlay with linear interconnect2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2018.8342171(1075-1080)Online publication date: Mar-2018
https://doi.org/10.23919/DATE.2018.8342171
Monson JHutchings B(2018)Enhancing debug observability for HLS-based FPGA circuits through source-to-source compilationJournal of Parallel and Distributed Computing10.1016/j.jpdc.2018.02.012117:C(148-160)Online publication date: 1-Jul-2018
https://dl.acm.org/doi/10.1016/j.jpdc.2018.02.012
Arato PSuba G(2014)A data flow graph generation method starting from c description by handling loop nest hierarchy2014 IEEE 9th IEEE International Symposium on Applied Computational Intelligence and Informatics (SACI)10.1109/SACI.2014.6840074(269-274)Online publication date: May-2014
https://doi.org/10.1109/SACI.2014.6840074

Index Terms

Hardware design space exploration using HercuLeS HLS
1. Hardware

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Information

Published In

cover image ACM Other conferences

PCI '13: Proceedings of the 17th Panhellenic Conference on Informatics

September 2013

359 pages

ISBN:9781450319690

DOI:10.1145/2491845

General Chairs:
Panayiotis H. Ketikidis
Greek Computer Society
,
Kostas Margaritis
University of Macedonia
,
Ioannis Vlahavas
Aristotle University of Thessaloniki
,
Program Chairs:
Alexandros Chatzigeorgiou
University of Macedonia
,
George Eleftherakis
The University of Sheffield
,
Ioannis Stamelos
Aristotle University of Thessaloniki

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

Sponsors

University of Macedonia
Aristotle University of Thessaloniki
The University of Sheffield: The University of Sheffield
Alexander TEI of Thessaloniki

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 September 2013

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PCI 2013

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The University of Sheffield

PCI 2013: 17th Panhellenic Conference on Informatics

September 19 - 21, 2013

Thessaloniki, Greece

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Cited By

Li XJain AMaskell DFahmy S(2018)A time-multiplexed FPGA overlay with linear interconnect2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2018.8342171(1075-1080)Online publication date: Mar-2018
https://doi.org/10.23919/DATE.2018.8342171
Monson JHutchings B(2018)Enhancing debug observability for HLS-based FPGA circuits through source-to-source compilationJournal of Parallel and Distributed Computing10.1016/j.jpdc.2018.02.012117:C(148-160)Online publication date: 1-Jul-2018
https://dl.acm.org/doi/10.1016/j.jpdc.2018.02.012
Arato PSuba G(2014)A data flow graph generation method starting from c description by handling loop nest hierarchy2014 IEEE 9th IEEE International Symposium on Applied Computational Intelligence and Informatics (SACI)10.1109/SACI.2014.6840074(269-274)Online publication date: May-2014
https://doi.org/10.1109/SACI.2014.6840074

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