Hierarchical Clustering for On-Chip Networks
Article No.: 2, Pages 1 - 6
Abstract
Hierarchy and communication locality are a must for many-core systems. As systems scale to dozens or hundreds of cores, we simply cannot afford the power consumption and latency of random communication that spans the entire chip. Existing hierarchical Networks-on-Chip (NoCs) support communication locality only for a fixed cluster of nodes; providing a fixed hierarchy is too restrictive in terms of parallelism and data placement. Therefore, we propose a new, more flexible class of hierarchical NoCs: Elastic Hierarchical NoCs. Elastic Hierarchical NoCs dynamically adjust the number and size of clusters during runtime according to the system's communication demands. The interconnect can adapt to changes in communication locality across different application phases, between applications and in the presence of server consolidation. Our design improves overall system performance by up to 46% and 13% on average over a conventional 2D mesh and by up to 16% and 6% on average over an existing hierarchical NoC implementation. Power consumption is reduced by 45% and 7% respectively on average.
References
[1]
C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC Benchmark Suite: Characterization and Architectural Implications. In Proc. of PACT, Oct. 2008.
[2]
S. Bourduas and Z. Zilic. A hybrid ring/mesh interconnect for network-on-chip using hierarchical rings for global routing. In NOCS, 2007.
[3]
J. Carmona, J. Cortadella, M. Kishinevsky, and A. Taubin. Elastic Circuits. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 28(10):1437--1455, Oct 2009.
[4]
W. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann, San Francisco, CA, 2003.
[5]
R. Das, S. Eachempati, A. Mishra, V. Narayanan, and C. Das. Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. In HPCA, pages 175 -- 186, 2009.
[6]
C. Fensch, N. Barrow-Williams, R. Mullins, and S. Moore. Designing a physical locality aware coherence protocol for chip-multiprocessors. IEEE Trans. on Comp., PP(99):1, 2012.
[7]
A. Guerre, N. Ventroux, R. David, and A. Merigot. Hierarchical network-on-chip for embedded many-core architectures. In Proc. of NOCS, pages 189--196, 2010.
[8]
N. Hardavellas, M. Ferdman, B. Falsafi, and A. Ailamaki. Reactive nuca: near-optimal block placement and replication in distributed caches. In ISCA, pages 184--195, 2009.
[9]
M. K. Jeong, D. H. Yoon, D. Sunwoo, M. Sullivan, I. Lee, and M. Erez. Balancing dram locality and parallelism in shared memory cmp systems. In Proc. of HPCA, pages 1 -- 12, feb. 2012.
[10]
M. M. Kim, J. D. Davis, M. Oskin, and T. Austin. Polymorphic On-Chip Networks. In ISCA, 2008.
[11]
M. Modarressi, A. Tavakkol, and H. Sarbazi-Azad. Application-aware topology reconfiguration for on-chip networks. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 19(11):2010 -- 2022, nov. 2011.
[12]
N. Neelakantam, C. Blundell, J. Devietti, M. M. Martin, and C. Zilles. FeS2: A Full-system Execution-driven Simulator for x86. Poster presented at ASPLOS 2008, 2008.
[13]
N. Nikitin, J. de San Pedro, J. Carmona, and J. Cortadella. Analytical performance modeling of hierarchical interconnect fabrics. In Proc of NOCS, 2012.
[14]
G. Ravindran and M. Stumm. A performance comparison of hierarchical ring- and mesh-connected multiprocessor networks. In Proc. of HPCA, 1997.
[15]
C. Sun, C.-H. O. Chen, G. Kurian, L. Wei, J. Miller, A. Agarwal, L.-S. Peh, and V. Stojanovic. DSENT - a tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling. In Proc. of the International Symposium on Networks-on-Chip, May 2012.
[16]
A. Udipi, N. Muralimanohar, and R. Balasubramonian. Towards scalable, energy-efficient, bus-based on-chip networks. In HPCA, 2010.
[17]
E. Zhang, Y. Jiang, and X. Shen. The significant of CMP cache sharing on contemporary multithreaded applications. IEEE Trans. on Parallel and Distributed Systems, 23(2), 2012.
- Hierarchical Clustering for On-Chip Networks
Recommendations
An analysis of on-chip interconnection networks for large-scale chip multiprocessors
With the number of cores of chip multiprocessors (CMPs) rapidly growing as technology scales down, connecting the different components of a CMP in a scalable and efficient way becomes increasingly challenging. In this article, we explore the ...
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic networks-on-chip (NoC) as a solution to reduce the impact of intra-chip ...
Leveraging dark silicon to optimize networks-on-chip topology
This paper presents a reconfigurable network-on-chip (NoC) for many-core chip multiprocessors (CMPs) in the dark silicon era, where a considerable part of high-end chips cannot be powered up due to the power and bandwidth walls. Core specialization, ...
Comments
Information & Contributors
Information
Published In
January 2016
53 pages
ISBN:9781450340847
DOI:10.1145/2857058
Copyright © 2016 ACM.
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]
In-Cooperation
- HiPEAC: HiPEAC Network of Excellence
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 18 January 2016
Check for updates
Author Tags
Qualifiers
- Research-article
- Research
- Refereed limited
Conference
AISTECS '16
AISTECS '16: 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems
January 18, 2016
Prague, Czech Republic
Acceptance Rates
Overall Acceptance Rate 7 of 8 submissions, 88%
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 143Total Downloads
- Downloads (Last 12 months)3
- Downloads (Last 6 weeks)0
Reflects downloads up to 10 Aug 2024
Other Metrics
Citations
View Options
Get Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in