Article

Polymorphic On-Chip Networks

Authors:

Martha Mercaldi Kim,

Mark Oskin, and

Todd AustinAuthors Info & Claims

ISCA '08: Proceedings of the 35th Annual International Symposium on Computer Architecture

June 2008

Pages 101 - 112

https://doi.org/10.1109/ISCA.2008.25

Published: 01 June 2008 Publication History

Abstract

As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We begin this study with an area-performance analysis of the interconnect design space. We find that there is no single network design that yields optimal performance across a range of traffic patterns. This indicates that there is an opportunity to gain performance by customizing the interconnect to a particular application or workload. We propose polymorphic on-chip networks to enable per-application network customization. This network can be configured prior to application runtime, to have the topology and buffering of arbitrary network designs. This paper proposes one such polymorphic network architecture. We demonstrate its modes of configurability, and evaluate the polymorphic network architecture design space, producing polymorphic fabrics that minimize the network area overhead. Finally, we expand the network on chip design space to include a polymorphic network design, showing that a single polymorphic network is capable of implementing all of the pareto optimal fixed-network designs.

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He XChen KFeng SKim HBlaauw DDreslinski RMudge TKloeckner AMoreira J(2022)Squaring the circleProceedings of the International Conference on Parallel Architectures and Compilation Techniques10.1145/3559009.3569665(148-159)Online publication date: 8-Oct-2022
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Index Terms

Polymorphic On-Chip Networks

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Information

Published In

cover image ACM Conferences

ISCA '08: Proceedings of the 35th Annual International Symposium on Computer Architecture

June 2008

449 pages

ISBN:9780769531748

ACM SIGARCH Computer Architecture News Volume 36, Issue 3
June 2008
449 pages
ISSN:0163-5964
DOI:10.1145/1394608
Issue’s Table of Contents

Sponsors

SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 June 2008

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ISCA08

Sponsor:

SIGARCH

ISCA08: The 35th Annual International Symposium on Computer Architecture

June 21 - 25, 2008

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ISCA '08 Paper Acceptance Rate 37 of 259 submissions, 14%;

Overall Acceptance Rate 543 of 3,203 submissions, 17%

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ISCA '25

Sponsor:
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The 52nd Annual International Symposium on Computer Architecture

June 21 - 25, 2025

Tokyo , Japan

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Cited By

He XChen KFeng SKim HBlaauw DDreslinski RMudge TKloeckner AMoreira J(2022)Squaring the circleProceedings of the International Conference on Parallel Architectures and Compilation Techniques10.1145/3559009.3569665(148-159)Online publication date: 8-Oct-2022
https://dl.acm.org/doi/10.1145/3559009.3569665
Zheng HWang KLouri ALi Z(2020)A versatile and flexible chiplet-based system design for heterogeneous manycore architecturesProceedings of the 57th ACM/EDAC/IEEE Design Automation Conference10.5555/3437539.3437654(1-6)Online publication date: 20-Jul-2020
https://dl.acm.org/doi/10.5555/3437539.3437654
Nematollahi NSadrosadati MFalahati HBarkhordar MDrumond MSarbazi-Azad HFalsafi B(2020)Efficient Nearest-Neighbor Data Sharing in GPUsACM Transactions on Architecture and Code Optimization10.1145/342998118:1(1-26)Online publication date: 30-Dec-2020
https://dl.acm.org/doi/10.1145/3429981
Pal SFeng SPark DKim SAmarnath AYang CHe XBeaumont JMay KXiong YKaszyk KMorton JSun JO'Boyle MCole MChakrabarti CBlaauw DKim HMudge TDreslinski RSarkar VKim H(2020)TransmuterProceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques10.1145/3410463.3414627(175-190)Online publication date: 30-Sep-2020
https://dl.acm.org/doi/10.1145/3410463.3414627
Hesse RJerger N(2016)Hierarchical Clustering for On-Chip NetworksProceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems10.1145/2857058.2857064(1-6)Online publication date: 18-Jan-2016
https://dl.acm.org/doi/10.1145/2857058.2857064
Mehrvarzy PModarressi MSarbazi-Azad H(2016)Power- and performance-efficient cluster-based network-on-chip with reconfigurable topologyMicroprocessors & Microsystems10.1016/j.micpro.2016.03.00446:PB(122-135)Online publication date: 1-Oct-2016
https://dl.acm.org/doi/10.1016/j.micpro.2016.03.004
Kannan AJerger NLoh GPrvulovic M(2015)Enabling interposer-based disintegration of multi-core processorsProceedings of the 48th International Symposium on Microarchitecture10.1145/2830772.2830808(546-558)Online publication date: 5-Dec-2015
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Modarressi MTeimouri NSarbazi-azad H(2015)Improving the performance of packet-switched networks-on-chip by SDM-based adaptive shortcut pathsIntegration, the VLSI Journal10.1016/j.vlsi.2014.10.00350:C(193-204)Online publication date: 1-Jun-2015
https://dl.acm.org/doi/10.1016/j.vlsi.2014.10.003
Büter WOsewold CGregorek DGarcía-Ortiz AFettweis GNebel W(2014)DCMProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2617052(1-4)Online publication date: 24-Mar-2014
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Jerger NKannan ALi ZLoh GFlautner KWenisch TOzer EFerdman M(2014)NoC Architectures for Silicon Interposer SystemsProceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2014.61(458-470)Online publication date: 13-Dec-2014
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