research-article

ConGen: An Application Specific DRAM Memory Controller Generator

Authors:

Deepak M. Mathew,

Christian Weis,

Irene Heinrich,

Marco V. Natale, and

Sven O. KrumkeAuthors Info & Claims

MEMSYS '16: Proceedings of the Second International Symposium on Memory Systems

October 2016

Pages 257 - 267

https://doi.org/10.1145/2989081.2989131

Published: 03 October 2016 Publication History

Abstract

The increasing gap between the bandwidth requirements of modern Systems on Chip (SoC) and the I/O data rate delivered by Dynamic Random Access Memory (DRAM), known as the Memory Wall, limits the performance of today's data-intensive applications. General purpose memory controllers use online scheduling techniques in order to increase the memory bandwidth. Due to a limited buffer depth they only have a local view on the executed application. However, numerous applications possess regular or fixed memory access patterns, which are not yet exploited to overcome the memory wall. In this paper, we present a holistic methodology to generate an Application Specific Memory Controller (ASMC), which has a global view on the application and utilizes application knowledge to decrease the energy and increase the bandwidth. To generate an ASMC we analyze the DRAM access pattern of the application offline and generate a custom address mapping by solving a combinatorial sequence partitioning problem.

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Thieu GGesper SPayá-Vayá GRiggers CRenke OFiedler TMarten JStuckenberg TBlume HWeis CSteiner LSudarshan CWehn NReimann LLeupers RBeyer MKöhler DJauch ABorrmann JJaberansari SBerthold TBlawat MKock MSchewior GBenndorf JKautz FBluethgen HSauer C(2023)ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10136978(1-6)Online publication date: Apr-2023
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Steiner LDelazeri GPrando da Silva IJung MWehn N(2023)Automatic DRAM Subsystem Configuration with iraceProceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems10.1145/3579170.3579259(66-72)Online publication date: 17-Jan-2023
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Li XYuan ZGuan YSun GZhang TWei RNiu D(2022)Flatfish: A Reinforcement Learning Approach for Application-Aware Address MappingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.314620441:11(4758-4770)Online publication date: Nov-2022
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ConGen: An Application Specific DRAM Memory Controller Generator
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    1. Semiconductor memory

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MEMSYS '16: Proceedings of the Second International Symposium on Memory Systems

October 2016

463 pages

ISBN:9781450343053

DOI:10.1145/2989081

General Chair:
Bruce Jacob
University of Maryland

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 03 October 2016

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Deutsche Forschungsgemeinschaft
Carl-Zeiss-Stiftung

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MEMSYS '16

MEMSYS '16: The Second International Symposium on Memory Systems

October 3 - 6, 2016

VA, Alexandria, USA

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https://doi.org/10.23919/DATE56975.2023.10136978
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https://dl.acm.org/doi/10.1145/3579170.3579259
Li XYuan ZGuan YSun GZhang TWei RNiu D(2022)Flatfish: A Reinforcement Learning Approach for Application-Aware Address MappingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.314620441:11(4758-4770)Online publication date: Nov-2022
https://doi.org/10.1109/TCAD.2022.3146204
Steiner LJung MPrado FBykov KWehn N(2022)DRAMSys4.0: An Open-Source Simulation Framework for In-depth DRAM AnalysesInternational Journal of Parallel Programming10.1007/s10766-022-00727-450:2(217-242)Online publication date: 12-Mar-2022
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Wei RLi CChen CSun GHe M(2021)Memory Access Optimization of a Neural Network Accelerator Based on Memory ControllerElectronics10.3390/electronics1004043810:4(438)Online publication date: 10-Feb-2021
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Asiatici MIenne P(2021)Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/346682315:2(1-33)Online publication date: 1-Dec-2021
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Natale MJung MKraft KLauer FFeldmann JSudarshan CWeis CKrumke SWehn N(2020)Efficient Generation of Application Specific Memory ControllersProceedings of the International Symposium on Memory Systems10.1145/3422575.3422796(233-247)Online publication date: 28-Sep-2020
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Stathis DSudarshan CYang YJung MWeis CHemani ALansner AWehn N(2020)eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale CortexJournal of Signal Processing Systems10.1007/s11265-020-01562-x92:11(1323-1343)Online publication date: 7-Jul-2020
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