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PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations

Published: 08 October 2002 Publication History

Abstract

Chip fabrication technology continues to plunge deeper into sub-micron levels requiring hardware designers to utilize ever-increasing amounts of logic and shorten design time. Toward that end, high-level languages such as C/C++ are becoming popular for hardware description and synthesis in order to more quickly leverage complex algorithms. Similarly, as logic density increases due to technology, power dissipation becomes a progressively more important metric of hardware design. PACT HDL, a C to HDL compiler, merges automated hardware synthesis of high-level algorithms with power and performance optimizations and targets arbitrary hardware architectures, particularly in a System on a Chip (SoC) setting that incorporates reprogrammable and application-specific hardware. PACT HDL is intended for applications well suited to custom hardware implementation such as image and signal processing codes. By making the compiler modular and flexible, optimizations may be executed in any order and at different levels in the compilation process. PACT HDL generates industry standard HDL codes, such as RTL Verilog and VHDL, which may be synthesized and profiled for power using commercial tools. This is the first paper on the PACT compiler project in a series. The compiler framework and introductory optimizations are presented. Later papers will focus on these and other optimizations in detail.

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Cited By

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  • (2013)An Improved FPGAs-Based Loop Pipeline Scheduling Algorithm for Reconfigurable CompilerRevised Selected Papers of the 10th International Symposium on Advanced Parallel Processing Technologies - Volume 829910.1007/978-3-642-45293-2_23(307-318)Online publication date: 27-Aug-2013
  • (2009)A design automation and power estimation flow for RFID systemsACM Transactions on Design Automation of Electronic Systems10.1145/1455229.145523614:1(1-31)Online publication date: 23-Jan-2009
  • (2007)A model-based extensible framework for efficient application design using FPGAACM Transactions on Design Automation of Electronic Systems10.1145/1230800.123080512:2(13-es)Online publication date: 1-Apr-2007
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cover image ACM Conferences
CASES '02: Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
October 2002
324 pages
ISBN:1581135750
DOI:10.1145/581630
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 08 October 2002

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Author Tags

  1. ASIC
  2. FPGA
  3. FSM
  4. HDL
  5. IP
  6. SoC
  7. VHDL
  8. Verilog
  9. compiler
  10. high-performance
  11. levelization
  12. low-power
  13. pipelining
  14. synthesis

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Cited By

View all
  • (2013)An Improved FPGAs-Based Loop Pipeline Scheduling Algorithm for Reconfigurable CompilerRevised Selected Papers of the 10th International Symposium on Advanced Parallel Processing Technologies - Volume 829910.1007/978-3-642-45293-2_23(307-318)Online publication date: 27-Aug-2013
  • (2009)A design automation and power estimation flow for RFID systemsACM Transactions on Design Automation of Electronic Systems10.1145/1455229.145523614:1(1-31)Online publication date: 23-Jan-2009
  • (2007)A model-based extensible framework for efficient application design using FPGAACM Transactions on Design Automation of Electronic Systems10.1145/1230800.123080512:2(13-es)Online publication date: 1-Apr-2007
  • (2007)An overview of a compiler for mapping software binaries to hardwareIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.90409515:11(1177-1190)Online publication date: 1-Nov-2007
  • (2006)Exploring power reduction options for a single-chip multiprocessor through system-level modelingJournal of Embedded Computing10.5555/1370998.13710012:2(235-247)Online publication date: 1-Apr-2006
  • (2006)Reducing power while increasing performance with superciscACM Transactions on Embedded Computing Systems10.1145/1165780.11657855:3(658-686)Online publication date: Aug-2006
  • (2005)Leakage power optimization with dual-Vth library in high-level synthesisProceedings of the 42nd annual Design Automation Conference10.1145/1065579.1065634(202-207)Online publication date: 13-Jun-2005
  • (2005)Behavioral Synthesis of Data-Dominated Circuits for Minimal Energy ImplementationProceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design10.1109/ICVD.2005.62(267-273)Online publication date: 3-Jan-2005
  • (2005)Leakage power optimization with dual-V/sub th/ library in high-level synthesisProceedings. 42nd Design Automation Conference, 2005.10.1109/DAC.2005.193801(202-207)Online publication date: 2005
  • (2004)Automatic translation of software binaries onto FPGAsProceedings of the 41st annual Design Automation Conference10.1145/996566.996678(389-394)Online publication date: 7-Jun-2004
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