research-article

The Olympus Synthesis System

Authors:

Giovanni De Micheli,

Frederic Mailhot,

Thomas TruongAuthors Info & Claims

IEEE Design & Test, Volume 7, Issue 5

Pages 37 - 53

https://doi.org/10.1109/54.60605

Published: 01 September 1990 Publication History

Abstract

A description is given of the Olympus synthesis system for digital design, a vertically integrated set of tools for multilevel synthesis, technology mapping, and simulation. The system includes behavioral, structural, and logic synthesis tools, and provides technology mapping and simulation. Since it is targeted for semicustom implementations, its output is in terms of gate netlists. Instead of supporting placement and routing tools, Olympus provides an interface to standard physical design tools. The system supports the synthesis of ASICs (application specific integrated circuits) from behavioral descriptions written in a hardware description language called HardwareC. Two internal models represent the hardware at different levels of abstraction and provide a way to pass design information among different tools. Olympus has been used to design three ASIC chips, and has been tested against benchmark circuits for high-level and logic synthesis.

References

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1. S. Lis and D. Gajski, "VHDL Synthesis using Structured Modeling," Proc. Design Automation Conf., 1989, pp. 606- 609.

Digital Library

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2. J. Rabaey et al., "Cathedral II: A Synthesis System for Multiprocessor DSP Systems," in Silicon Compilation, D. Gajski, ed., Addison Wesley, Reading, Mass., 1988, pp. 311-360.

[3]

3. D. Thomas et al., Algorithmic and Register-Transfer Level Synthesis: The Systems Architect's Workbench, Kluwer Academic Press, Boston, 1989.

Digital Library

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4. A. Parker, J. Pizarro, and M. Mlinar, "MAHA: A Program for Data Path Synthesis," Proc. Design Automation Conf., 1986, pp. 461-466.

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5. Design Systems for VLSI Circuits: Logic Synthesis and Silicon Compilation, G. De Micheli, A. Sangiovanni-Vincentelli, and P. Antognetti, eds., Martinus Nijhoff, Dordrecht, The Netherlands, 1987.

[6]

6. D. Gajski, Silicon Compilation, Addison Wesley, Reading, Mass., 1988.

[7]

1. D. Ku and G. De Micheli, HardwareC: A Language for Hardware Design, tech. rpt. CSL-TR-90-419, Computer System Lab., Stanford Univ., Aug. 1990 (Version 2.0).

Digital Library

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2. D. Ku and G. De Micheli, "High Level Synthesis and Optimization Strategies in Hercules and Hebe," Proc. European ASIC Conf., 1990, pp. 124-129.

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3. R. Brayton et al., "MIS: A Multiple-Level Logic Optimization System," IEEE Trans. Computer-Aided Design, Vol. CAD-6, No. 6, Nov. 1987, pp. 1062-1081.

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4. R. Camposano and W. Rosenstiel, "Synthesizing Circuits from Behavioral Descriptions," IEEE Trans. Computer-Aided Design, Vol. CAD-8, No. 1, Feb. 1989, pp. 171-180.

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5. M. McFarland, "Using Bottom-Up Design Techniques in the Synthesis of Digital Hardware from Abstract Behavioral Descriptions," Proc. Design Automation Conf., 1986, pp. 474-480.

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6. D. Ku and G. De Micheli, Relative Scheduling Under Timing Constraints, tech rpt. CSL-TR-89-401, Stanford University, Stanford, Calif., Nov. 1989: also in Proc. Design Automation Conf., 1990, pp. 59-64.

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7. F. Mailhot and G. De Micheli, "Technology Mapping Using Boolean Matching and Don't Care Sets," Proc. European Design Automation Conf., Mar. 1990, pp. 212-216.

Digital Library

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8. K. Keutzer, "Technology Binding and Local Optimization by DAG Matching," Proc. Design Automation Conf., 1987, pp. 341-347.

Digital Library

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9. V. Rampa and G. De Micheli, "Computer-Aided Synthesis of a Discrete Cosine Transform Chip," Proc. Int'l Symp. Circuits and Systems, 1989, pp. 220-225.

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10. M. Ligthart et al. "Design of a Digital Audio Input Output Chip," Proc. Custom Integrated Circuit Conf., 1989, pp. 15.1.1-15.1.6.

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11. D. Kasle, "High Resolution Decoding Techniques and Single-Chip Decoders for Multi-Anode Microchannel Arrays," Proc. Int'l Soc. for Optical Eng., Vol. 1158, Aug. 1989, pp. 311-318.

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12. F. Mailhot and G. De Micheli, "Automatic Layout and Optimization of Static CMOS Cells," Proc. Int'l Conf. Computer Design, 1988, pp. 180-185.

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Edwards S(2005)The Challenges of Hardware Synthesis from C-Like LanguagesProceedings of the conference on Design, Automation and Test in Europe - Volume 110.1109/DATE.2005.307(66-67)Online publication date: 7-Mar-2005
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cover image IEEE Design & Test

IEEE Design & Test Volume 7, Issue 5

September 1990

56 pages

ISSN:0740-7475

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Copyright © Copyright © 1990 IEEE. All Rights Reserved.

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 September 1990

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Cited By

Hoare RJones AKusic DFazekas JFoster JTung SMcCloud M(2006)Rapid VLIW processor customization for signal processing applications using combinational hardware functionsEURASIP Journal on Advances in Signal Processing10.1155/ASP/2006/464722006(67-67)Online publication date: 1-Jan-2006
https://dl.acm.org/doi/10.1155/ASP/2006/46472
Edwards S(2006)The Challenges of Synthesizing Hardware from C-Like LanguagesIEEE Design & Test10.1109/MDT.2006.13423:5(375-386)Online publication date: 1-Sep-2006
https://dl.acm.org/doi/10.1109/MDT.2006.134
Edwards S(2005)The Challenges of Hardware Synthesis from C-Like LanguagesProceedings of the conference on Design, Automation and Test in Europe - Volume 110.1109/DATE.2005.307(66-67)Online publication date: 7-Mar-2005
https://dl.acm.org/doi/10.1109/DATE.2005.307
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Jones ABagchi DPal STang XChoudhary ABanerjee PBhattacharyya SMudge TWolf WJerraya A(2002)PACT HDLProceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/581630.581659(188-197)Online publication date: 8-Oct-2002
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Gupta RCoelho CDe Micheli G(2001)Synthesis and simulation of digital systems containing interacting hardware and software componentsReadings in hardware/software co-design10.5555/567003.567051(544-549)Online publication date: 1-Jun-2001
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Balboni AFornaciari WSciuto D(2001)Co-synthesis and co-simulation of control-dominated embedded systemsReadings in hardware/software co-design10.5555/567003.567038(395-411)Online publication date: 1-Jun-2001
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De Micheli GGupta R(2001)Hardware/software co-designReadings in hardware/software co-design10.5555/567003.567007(30-44)Online publication date: 1-Jun-2001
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Ernst RHenkel JBenner T(2001)Hardware-software cosynthesis for microcontrollersReadings in hardware/software co-design10.5555/567003.567006(18-29)Online publication date: 1-Jun-2001
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Gupta RDe Micheli G(2001)Hardware-software cosynthesis for digital systemsReadings in hardware/software co-design10.5555/567003.567005(5-17)Online publication date: 1-Jun-2001
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