- Conference Chair:
- Rolf Ernst
On behalf of the ICCAD 2001 Executive and Technical Program committees, I would like to welcome you to the International Conference on Computer-Aided Design which will take place November 4 - 8 at the San Jose DoubleTree Hotel.The main part of the ICCAD program consists of 30 technical paper sessions. The 92 papers which will be presented in these sessions were selected from 301 paper submissions. The technical paper sessions are complemented by 5 embedded tutorials, each giving an overview on the most recent developments in an emerging or hot topic presented by leading experts in the field. This time, the embedded tutorials cover embedded software & systems, platform based design, RF and analog synthesis, power design issues, and EDA problems of MEMS design. A panel on Wednesday afternoon titled "Automatic Hierarchical Design: Fantasy or Reality?" will discuss the highly controversial matter of hierarchical versus flat design.A core task of forward looking EDA research is the observation of long term trends in design technologies to timely identify upcoming challenges and opportunities for EDA tools and methodologies. As a novel approach to increase the awareness of the EDA community for such trends, ICCAD 2001 has invited key experts to introduce and discuss materials, circuits, architectures, and design issues of nanotechnologies. The keynote, "Nanotechnology and the Information Age" by Thomas Theis, Director of Physical Sciences at IBM Research, will be followed by a panel: "Will Nanotechnology Change the Way We Design and Verify Systems?" on Monday evening, bringing together experts from different areas of this exciting research field.This technical program has been organized by the Program Chair, Larry Pileggi, and by the Vice Program Chair, Andreas Kuehlmann, with the support of the Program and the Executive Committees.Thursday, November 8, brings a new set of the very successful series of ICCAD full-day tutorials. They were organized by our tutorial chair, Hidetoshi Onodera, and will cover the topics 1) Low-Power Embedded Software: What, Why, and How? 2) Optimization Strategies for Physical Synthesis and Timing Closure 3) Signal Integrity (new edition of the best selling tutorial of ICCAD 2000) 4) Boolean Satisfiability.I hope you will enjoy the conference and experience some of the enthusiasm and excitement which spurs our research community to accept the ever increasing challenges of EDA in the deep submicron design age.
Congestion aware layout driven logic synthesis
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitioning and clustering algorithms to achieve faster turn around times.With the ...
Addressing the timing closure problem by integrating logic optimization and placement
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation, logic synthesis and layout synthesis are iterated until the estimates ...
An algorithm for simultaneous pin assignment and routing
Macro-block pin assignment and routing are important tasks in physical design planning. Existing algorithms for these problems can be classified into two categories: 1) a two-step approach where pin assignment is followed by routing, and 2) a net-by-net ...