IEEE Design & Test

With increased technology scaling, high variability and low reliability will likely be the main challenges for chip design and testing. This issue discusses some of the key issues for handling increasing variations and uncertainties. Also, D&T's plans ...

As silicon manufacturing processes scale to and beyond the 65-nm node, process variations are consuming an increasingly larger portion of design and test budgets. Such variations play a significant part in subthreshold leakage and other important device ...

As device technology progresses toward 45 nm and beyond, the fidelity of process parameter modeling becomes questionable. The authors propose the concept of process variation (PV) testing, which involves applying an innovative fault model and test ...

Because of the significant cost of explicitly testing an integrated, heterogeneous device for all its specifications, there is a need for a test methodology that minimizes test cost while maintaining product quality and limiting yield loss. The authors ...

Today's consumer electronics must be portable, reliable at various operating environments, and power efficient. Thus, semiconductor manufacturers constantly upgrade their production technologies and incorporate intelligent circuit design techniques. ...

With each successive technology generation, process and environmental variations consume an increasingly large portion of the design envelope. To mitigate the impact of these variations, designs can incorporate adaptive techniques to reduce the impact. ...

With continued technology scaling, silicon is becoming increasingly less predictable. Recent years have brought an acceleration of wear-out mechanisms, such as oxide breakdown and NBTI, which occur over a part's lifetime. Manufacturing device failure ...

An interview with Hans Stork, Chief Technology Officer of Texas Instruments. Ken Wagner, the IEEE Design & Test interviews editor, speaks to TI's Hans Stork during the 2006 Design Automation Conference. In this in-depth interview, Stork tells us about ...

This is a review of Networks on Chips: Technology and Tools, by Giovanni De Micheli and Luca Benini. This comprehensive survey and integrated reference work on networks on chips (NoCs) offers both breadth in covering most of the major work in this area ...

The "Design and test on chip for EMC" panel at the 2006 EMC Europe International Symposium on Electromechanical Compatibility addressed the recent explosion of the portable-electronics market and the increasingly hostile electromagnetic environment in ...

This report discusses the 2006 IEEE East-West Design & Test International Workshop, held 15 to 19 September 2006 in Sochi, Russia. The goal of the workshop was to exchange experience in design and test of electronic systems among scientific experts from ...

This newsletter covers news, research, and events related to the IEEE Council on Electronic Design Automation.

This newsletter provides information on past and upcoming events related to the IEEE Computer Society's Test Technology Technical Council and the test community.

This newsletter provides news, events, and information related to the IEEE Computer Society's Design Automation Technical Committee and the EDA community.

This index includes all items appearing in IEEE Design & Test during 2006 that are considered to have archival value.

Variability and reliability will be the barriers to future technology scaling. Every discipline, from fabrication to software, needs to cooperate and make the VLSI system reliable in the presence of variability and the resulting inherent unreliability ...