IEEE Design & Test

This issue of IEEE Design & Test discusses some of the challenges of electronic system-level design and their corresponding solutions. In addition, a special section highlights the 2006 International Test Conference.

ESL, or electronic-system level, has found its way into the mainstream EDA vocabulary in the past few years because of increased interest in finding new ways to raise the abstraction level for the design entry point during the electronic-systems design ...

This article focuses on two key properties that the authors see as critical to ESL design: abstraction and reuse. The authors present an ESL design flow using the Gezel language. Using several very different design examples, they show how this design ...

This article addresses the need for directly expressing heterogeneous, hierarchical behaviorsfor modeling specific embedded systems. After analyzing two existing ESL languages, SystemC andEsterel, the authors created a new model of computation and a ...

This article presents a taxonomy for ESL tools and methodologies that combines UC Berkeley'splatform-based design terminologies with Dan Gajski's Y-chart work. This is timely and necessarybecause in the ESL world we seem to be building tools without ...

This article presents one side of an ongoing debate on the appropriateness of C-like languages as hardware description languages. The article examines various features of C and their mapping to hardware, and makes a cogent argument that vanilla C is not ...

Contrary to Stephen Edwards' article, "The Challenges of Synthesizing Hardware from C-Like Languages," this article details the benefits of SystemC for hardware synthesis.

This special section, along with the International Test Conference 2006, highlights the value that test adds to the electronics manufacturing business. It leads us to think about test in a whole new way.

Defect density and size distributions are difficult to characterize, especially if you havelittle or no access to test vehicles specifically designed for the purpose. The authors propose a newmethodology for extracting that information directly from ...

Structured delay test using scan transition tests is becoming commonplace. But high coverage andcompact tests can still be elusive in some situations. The authors propose a novel techniquecombining the cost-effectiveness of launch-from-capture test with ...

It is a well-known phenomenon that test-mode switching activity and power consumption can exceed that of mission mode. Thus, testing can induce localized heating and temperature gradients with deleterious results. The authors quantify this problem and ...

This newsletter provides information on past and upcoming events related to the IEEE Computer Society's Test Technology Technical Council and the test community.

A review of Electronic Design Automation for Integrated Circuits Handbook, edited by Louis Scheffer, Luciano Lavagno, and Grant Martin.

Two interesting standardization proposals, Rosetta and Esterel version 7, both are based ontechnology that has been under development for a long time, and both target the formalization ofsystem-level design and verification. But, otherwise, they take ...

This newletter provides information on developments, events, and news related to the Council on Electronic Design Automation. This installment features a conversation with Robert Brayton, recipient of the 2006 EDAA Lifetime Achievement Award and the ...

A look at plans for the 2006 International Test Conference.