Testing of Current Carrying Capacity of Conducting Tracks in High Power Flexible Printed Circuit Boards
In high power electronic applications, the current carrying conducting tracks of the printed circuit board (PCB) and the components generate heat. For the proper working of the circuit, this heat must be expelled to the surroundings. In flexible PCBs, ...
Memory-Aware Design Space Exploration for Reliability Evaluation in Computing Systems
In this paper, we present an analytical methodology to measure the vulnerability of the memory components of a microprocessor-based computing system. It is based on the data and the instruction lifetime and residence. The proposed approach considers ...
Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits
As the feature size of CMOS transistors scales down, Single Event Transient (SET) has been an important consideration in designing modern radiation tolerant circuits because it may cause some failures in the circuit outputs. Many researches have been ...
An Integrated on-Silicon Verification Method for FPGA Overlays
Field Programmable Gate Arrays (FPGAs) gain popularity as higher-level tools evolve to deliver the benefits of re-programmable silicon to engineers and scientists at all levels of expertise. In order to use FPGAs efficiently, new CAD tools and modern ...
Evaluating the Impact of Temperature on Dynamic Fault Behaviour of FinFET-Based SRAMs with Resistive Defects
In recent years, FinFET-based Static Random Access Memories (SRAMs) have become a viable solution to provide the storage of big data volume in Systems-on-Chip (SoCs) as well as to assure high performance deep-scaled devices. As consequence, FinFET-based ...
A Unified Approach to Detect and Distinguish Hardware Trojans and Faults in SRAM-based FPGAs
In recent years, confrontation with hardware Trojans has become a major concern due to various reasons including outsourcing. Such a growing threat is more pronounced in reconfigurable devices as they are used in widespread applications due to low ...
A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip
Networks-on-chip (NoC) provide the communication infrastructure for high-speed and large-scale computation that integrates several IP-cores on a single die. Faults on network channels severely degrade system performance and throughput. This paper ...
Characterization Method for Integrated Magnetic Devices at Lower Frequencies (up to 110 MHz)
Nowadays, the characterization of planar integrated components is a challenge. The objective is to characterize these devices on a broadband frequency (from a few Hz to a few GHz). Currently, these integrated devices cannot be characterized at low ...
Low-Cost Strategy for Bus Propagation Delay Reduction
We propose a strategy to reduce the propagation delay of microprocessors' digital bus lines at very low costs in terms of area overhead, power consumption and power-delay product. Likewise some solutions adopted in industry nowadays, our strategy ...
Impact of Bias Temperature Instability (BTI) Aging Phenomenon on Clock Deskew Buffers
In this paper we analyze the effect of the Bias Temperature Instability (BTI) aging phenomenon on the delay of deskew buffers employed in high performance microprocessors. Our analysis shows that, during circuit lifetime, the delay induced by BTI on ...
