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Rapid evaluation of custom instruction selection approaches with FPGA estimation
The main aim of this article is to demonstrate that a fast and accurate FPGA estimation engine is indispensable in design flows for custom instruction (template) selection. The need for a FPGA estimation engine stems from the difficulty in predicting ...
Task scheduling: A control-theoretical viewpoint for a general and flexible solution
This article presents a new approach to the design of task scheduling algorithms, where system-theoretical methodologies are used throughout. The proposal implies a significant perspective shift with respect to mainstream design practices, but yields ...
Elon: Enabling efficient and long-term reprogramming for wireless sensor networks
We present a new mechanism called Elon for enabling efficient and long-term reprogramming in wireless sensor networks. Elon reduces the transferred code size significantly by introducing the concept of replaceable component. It avoids the cost of ...
Bluetooth aided mobile phone localization: A nonlinear neural circuit approach
It is meaningful to design a strategy to roughly localize mobile phones without a GPS by exploiting existing conditions and devices especially in environments without GPS availability (e.g., tunnels, subway stations, etc.). The availability of Bluetooth ...
Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors
The recent emergence of various Non-Volatile Memories (NVMs), with many attractive characteristics such as low leakage power and high-density, provides us with a new way of addressing the memory power consumption problem. In this article, we target ...
Message blinding method requiring no multiplicative inversion for RSA
This article proposes a new message blinding methods requiring no multiplicative inversion for RSA. Most existing message blinding methods for RSA additionally require the multiplicative inversion, even though computational complexity of this operation ...
A Multiple-FPGA parallel computing architecture for real-time simulation of soft-object deformation
Hardware-based parallel computing is proposed for acceleration of finite-element (FE) analysis of linear elastic deformation models. An implementation of the Preconditioned Conjugate Gradient algorithm on N Field Programmable Gate Array (FPGA) devices ...
Building timing predictable embedded systems
- Philip Axer,
- Rolf Ernst,
- Heiko Falk,
- Alain Girault,
- Daniel Grund,
- Nan Guan,
- Bengt Jonsson,
- Peter Marwedel,
- Jan Reineke,
- Christine Rochange,
- Maurice Sebastian,
- Reinhard Von Hanxleden,
- Reinhard Wilhelm,
- Wang Yi
A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the challenge of ...
Embedded RAIDs-on-chip for bus-based chip-multiprocessors
The dual effects of larger die sizes and technology scaling, combined with aggressive voltage scaling for power reduction, increase the error rates for on-chip memories. Traditional on-chip memory reliability techniques (e.g., ECC) incur significant ...
Python to accelerate embedded SoC design: A case study for systems biology
We present SysPy (System Python) a tool which exploits the strengths of the popular Python scripting language to boost design productivity of embedded System on Chips for FPGAs. SysPy acts as a “glue” software between mature HDLs, ready-to-use VHDL ...
A low-power instruction replay mechanism for design of resilient microprocessors
There is a growing concern about the increasing rate of defects in computing substrates. Traditional redundancy solutions prove to be too expensive for commodity microprocessor systems. Modern microprocessors feature multiple execution units to take ...
Simultaneous hardware and time redundancy with online task scheduling for low energy highly reliable standby-sparing system
Standby-sparing is one of the common techniques in order to design fault-tolerant safety-critical systems where the high level of reliability is needed. Recently, the minimization of energy consumption in embedded systems has attracted a lot of ...
Towards scalable arithmetic units with graceful degradation
This article presents a new family of scalable arithmetic units (ScAUs) targeting resource-constrained, embedded devices. We, first, study the performance, power, area and scalability properties of general adders. Next, suitable error-detection schemes ...
Adaptive wear-leveling algorithm for PRAM main memory with a DRAM buffer
Phase Change RAM (PRAM) is a candidate to replace DRAM main memory due to its low idle power consumption and high scalability. However, its latency and endurance have generated problems in fulfilling its main memory role. The latency can be treated with ...
Transport triggered architecture to perform carrier synchronization for LTE
In this article implementation of carrier frequency offset estimate for 20MHz LTE baseband processing is discussed. LTE (Long Term Evolution) is a wireless communication standard that makes use of some innovative techniques to gain very high data rates (...
An approach to manage reconfigurations and reduce area cost in hard real-time reconfigurable systems
This article presents a methodology for building real-time reconfigurable systems that ensures that all the temporal constraints of a set of applications are met while optimizing the utilization of the available reconfigurable resources. Starting from a ...
Bandwidth allocation for fixed-priority-scheduled compositional real-time systems
Recent research in compositional real-time systems has focused on determination of a component's real-time interface parameters. An important objective in interface-parameter determination is minimizing the bandwidth allocated to each component of the ...
Extended Instruction Exploration for Multiple-Issue Architectures
In order to satisfy the growing demand for high-performance computing in modern embedded devices, several architectural and microarchitectural enhancements have been implemented in processor architectures. Extended instruction (EI) is often used for ...
A study on parallelizing XML path filtering using accelerators
Publish-subscribe systems present the state of the art in information dissemination to multiple users. Such systems have evolved from simple topic-based to the current XML-based systems. XML-based pub-sub systems provide users with more flexibility by ...
Providing reliable and real-time delivery in the presence of body shadowing in breadcrumb systems
The primary goal of breadcrumb trail sensor networks is to transmit in real-time users' physiological parameters that measure life-critical functions to an incident commander through reliable multihop communication. In applications using breadcrumb ...
GPU-like on-chip system for decoding LDPC codes
Rapid prototyping is an important step in the development and the verification of computationally demanding tasks of digital communication systems, such as Forward Error Correction (FEC) decoding. The goal is to replace time-consuming simulations based ...
Online learning of timeout policies for dynamic power management
Dynamic power management (DPM) refers to strategies which selectively change the operational states of a device during runtime to reduce the power consumption based on the past usage pattern, the current workload, and the given performance constraint. ...
Simulation-based functional verification of dynamically reconfigurable systems
Dynamically reconfigurable systems (DRS) implemented using field-programmable gate arrays (FPGAs) allow hardware logic to be partially reconfigured while the rest of the design continues to operate. By mapping multiple reconfigurable hardware modules to ...
An asymmetric dual-processor architecture for low-power information appliances
As users become increasingly conscious of their energy footprint—either to improve battery life or to respect the environment—improved energy efficiency of systems has gained in importance. This is especially important in the context of information ...