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- ArticleJune 2001
Mismatch analysis and direct yield optimization by specwise linearization and feasibility-guided search
DAC '01: Proceedings of the 38th annual Design Automation ConferenceJune 2001, Pages 858–863https://doi.org/10.1145/378239.379079We present a new method for mismatch analysis and automatic yield optimization of analog integrated circuits with respect to global, local and operational tolerances. Effectiveness and efficiency of yield estimation and optimization are guaranteed by ...
- ArticleJune 2001
Power-aware scheduling under timing constraints for mission-critical embedded systems
DAC '01: Proceedings of the 38th annual Design Automation ConferenceJune 2001, Pages 840–845https://doi.org/10.1145/378239.379076Power-aware systems are those that must make the best use of available power. They subsume traditional low-power systems in that they must not only minimize power when the budget is low, but also deliver high performance when required. This paper ...
- ArticleJune 2001
Energy efficient fixed-priority scheduling for real-time systems on variable voltage processors
DAC '01: Proceedings of the 38th annual Design Automation ConferenceJune 2001, Pages 828–833https://doi.org/10.1145/378239.379074Energy consumption has become an increasingly important consideration in designing many real-time embedded systems. Variable voltage processors, if used properly, can dramatically reduce such system energy consumption. In this paper, we present a ...
- ArticleJune 2001
Fast statistical timing analysis by probabilistic event propagation
DAC '01: Proceedings of the 38th annual Design Automation ConferenceJune 2001, Pages 661–666https://doi.org/10.1145/378239.379043We propose a new statistical timing analysis algorithm, which produces arrival-time random variables for all internal signals and primary outputs for cell-based designs with all cell delays modeled as random variables. Our algorithm propagates ...
- ArticleJune 2001
Static schedluing of multiple asynchronous domains for functional verification
DAC '01: Proceedings of the 38th annual Design Automation ConferenceJune 2001, Pages 647–652https://doi.org/10.1145/378239.379040While ASIC devices of a decade ago primarily contained synchro-nous circuitry triggered with a single clock, many contemporary architectures require multiple clocks that operate asynchronously to each other. This multi-clock domain behavior presents ...
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- ArticleJune 2001
Integrating scheduling and physical design into a coherent compilation cycle for reconfigurable computing architectures
DAC '01: Proceedings of the 38th annual Design Automation ConferenceJune 2001, Pages 635–640https://doi.org/10.1145/378239.379038Advances in the FPGA technology, both in terms of device capacity and architecture, have resulted in introduction of reconfigurable computing machines, where the hardware adapts itself to the running application to gain speedup. To keep up with the ...
- ArticleJune 2001
Integrated high-level synthesis and power-net routing for digital design under switching noise constraints
DAC '01: Proceedings of the 38th annual Design Automation ConferenceJune 2001, Pages 629–634https://doi.org/10.1145/378239.379037This paper presents a CAD methodology and a tool for high-level synthesis (HLS) of digital hardware for mixed analog-digital chips. In contrast to HLS for digital applications, HLS for mixed-signal systems is mainly challenged by constraints, such as ...
- ArticleJune 2001
Model checking of S3C2400X industrial embedded SOC product
DAC '01: Proceedings of the 38th annual Design Automation ConferenceJune 2001, Pages 611–616https://doi.org/10.1145/378239.379034This paper describes our experience and methodology used in the model checking of S3C2400X industrial embedded SOC product. We employed model checking to verify the RTL implementation. We describe how to model the multiple clocks, gated clocks, ...
- ArticleJune 2001
System-level power/performance analysis for embedded systems design
DAC '01: Proceedings of the 38th annual Design Automation ConferenceJune 2001, Pages 599–604https://doi.org/10.1145/378239.379032This paper presents a formal technique for system-level power/performance analysis that can help the designer to select the right platform starting from a set of target applications. By platform we mean a family of heterogeneous architectures that ...
- ArticleJune 2001
Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit symmetric block ciphers
DAC '01: Proceedings of the 38th annual Design Automation ConferenceJune 2001, Pages 579–584https://doi.org/10.1145/378239.379027Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concurrent error detection (CED) architectures can be used to thwart such ...
- ArticleJune 2001
Fast power/ground network optimization based on equivalent circuit modeling
DAC '01: Proceedings of the 38th annual Design Automation ConferenceJune 2001, Pages 550–554https://doi.org/10.1145/378239.379021This paper presents an efficient algorithm for optimizing the area of power or ground networks in integrated circuits subject to the reliability constraints. Instead of solving the original power/ground networks extracted from circuit layouts as ...
- ArticleJune 2001
A framework for low complexitgy static learning
DAC '01: Proceedings of the 38th annual Design Automation ConferenceJune 2001, Pages 546–549https://doi.org/10.1145/378239.379020In this paper, we present a new data structure for a complete implication graph and two techniques for low complexity static learning. We show that using static indirect &Lgr-implications and super gate extraction some hard-to-detect static and dynamic ...
- ArticleJune 2001
SATIRE: a new incremental satisfiability engine
DAC '01: Proceedings of the 38th annual Design Automation ConferenceJune 2001, Pages 542–545https://doi.org/10.1145/378239.379019We introduce SATIRE, a new satisfiability solver that is particular-ly suited to verification and optimization problems in electronic de-sign automation. SATIRE builds on the most recent advances in satisfiability research, and includes two new features ...
- ArticleJune 2001
Dynamic detection and removal of inactive clauses in SAT with application in image computation
DAC '01: Proceedings of the 38th annual Design Automation ConferenceJune 2001, Pages 536–541https://doi.org/10.1145/378239.379018In this paper, we present a new technique for the efficient dynamic detection and removal of inactive clauses, i.e. clauses that do not affect the solutions of interest of a Boolean Satisfiability (SAT) problem. The algorithm is based on the extraction ...
- ArticleJune 2001
Chaff: engineering an efficient SAT solver
DAC '01: Proceedings of the 38th annual Design Automation ConferenceJune 2001, Pages 530–535https://doi.org/10.1145/378239.379017Boolean Satisfiability is probably the most studied of combinatorial optimization/search problems. Significant effort has been devoted to trying to provide practical solutions to this problem for problem instances encountered in a range of applications ...
- ArticleJune 2001
Watermarking graph partitioning solutions
DAC '01: Proceedings of the 38th annual Design Automation ConferenceJune 2001, Pages 486–489https://doi.org/10.1145/378239.378567Trends in the semiconductor industry towards extensive design and code reuse motivate a need for adequate Intellectual Property Protection (IPP) schemes. We offer a new general IPP scheme called constraint-based watermarking and analyize it in the ...
- ArticleJune 2001
Watermarking of SAT using combinatorial isolation lemmas
DAC '01: Proceedings of the 38th annual Design Automation ConferenceJune 2001, Pages 480–485https://doi.org/10.1145/378239.378566Watermarking of hardware and software designs is an effective mechanism for intellectual property protection (IPP). Two important criteria for watermarking schemes are credibility and fairness. In this paper, we present the unique solution-based ...
- ArticleJune 2001
Battery-aware static scheduling for distributed real-time embedded systems
DAC '01: Proceedings of the 38th annual Design Automation ConferenceJune 2001, Pages 444–449https://doi.org/10.1145/378239.378553This paper addresses battery-aware static scheduling in battery-powered distributed real-time embedded systems. As suggested by previous work, reducing the discharge current level and shaping its distribution are essential for extending the battery ...
- ArticleJune 2001
Low-energy intra-task voltage scheduling using static timing analysis
DAC '01: Proceedings of the 38th annual Design Automation ConferenceJune 2001, Pages 438–443https://doi.org/10.1145/378239.378551We propose an intra-task voltage scheduling algorithm for low-energy hard real-time applications. Based on a static timing analysis technique, the proposed algorithm controls the supply voltage within an individual task boundary. By fully exploiting all ...
- ArticleJune 2001
A new structural pattern matching algorithm for technology mapping
DAC '01: Proceedings of the 38th annual Design Automation ConferenceJune 2001, Pages 371–376https://doi.org/10.1145/378239.378526In this paper, a new structural matching algorithm for technology mapping is proposed. The algorithm is based on a key observation that the matches for a node in a subject Boolean network are related to the matches for its children. The structural ...