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Integrated high-level synthesis and power-net routing for digital design under switching noise constraints

Published: 22 June 2001 Publication History
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  • Abstract

    This paper presents a CAD methodology and a tool for high-level synthesis (HLS) of digital hardware for mixed analog-digital chips. In contrast to HLS for digital applications, HLS for mixed-signal systems is mainly challenged by constraints, such as digital switching noise (DSN), that are due to the analog circuits. This paper discusses an integrated approach to HLS and power net routing for effectively reducing DSN. Motivation for this research is that HLS has a high impact on DSN reduction, however, DSN evaluation is very difficult at a high level. Integrated approach also employs an original method for fast evaluation of DSN and an algorithm for power net routing and sizing. Experiments showed that our combined binding and scheduling method produces better results than traditional HLS techniques. Finally, DSN evaluation using the proposed algorithm can be significantly faster than SPICE simulation.

    References

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    X. Aragones et al, "Analysis and Solutions for Switched Noise Coupling in Mixed-Signal ICs", Kluwer, 1999.
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    R. Bergamaschi, "Behavioral Network Graph Unifying the Domains of High-Level and Logical Synthesis", Proc. of DAC, 1999.
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    K. Boese, A. Kahng, G. Robins, "High-Performance Routing Trees with Identified Critical Skins", Proc. of DAC, 1993.
    [4]
    E. Charbon et al, "Modeling Digital Substrate Noise Injection in Mixed-Signal IC's", IEEE Trans. on CADICS, Vol.18, No.3, March 1999, pp.301-310.
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    G. De Micheli, "Synthesis and Optimization of Digital Circuits", McGraw-Hill, 1994.
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    A. Doboli, "Specification and Design-Space Exploration for High-Level Synthesis of Analog and Mixed-Signal Systems", Ph.D. Thesis, University of Cincinnati, 2000.
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    W. Dougherty, D. Thomas, "Unifying Behavioral Synthesis and Physical Design", Proc. of DAC, 2000.
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    K. Joardar, "A Simple Approach to Modeling Cross-Talk in Integrated Circuits", IEEE JSSC, Vol. 29, no. 10, October 1994, pp. 1212-1219.
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    J. Nestor, G. Krishnamoorthy, "SALSA: A New Approach to Scheduling with Timing Constraints", IEEE Trans. on CADICS, May 1993.
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    P. G.Paulin, J. P. Knight, "Force Directed Scheduling for the Behavior Synthesis of ASICs", IEEE Trans. on CADICS, volume 8, June 1989, pp.661-679.
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    B. Stanisic et al, "Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs", Kluwer, 1996.

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    • (2020)A novel agent-based, evolutionary model for expressing the dynamics of creative open-problem solving in small groupsApplied Intelligence10.1007/s10489-020-01919-6Online publication date: 27-Oct-2020

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    cover image ACM Conferences
    DAC '01: Proceedings of the 38th annual Design Automation Conference
    June 2001
    863 pages
    ISBN:1581132972
    DOI:10.1145/378239
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    Published: 22 June 2001

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    • (2020)A novel agent-based, evolutionary model for expressing the dynamics of creative open-problem solving in small groupsApplied Intelligence10.1007/s10489-020-01919-6Online publication date: 27-Oct-2020

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