Article

Fast power/ground network optimization based on equivalent circuit modeling

Authors:

X.-D. Sheldon Tan,

C.-J. Richard ShiAuthors Info & Claims

DAC '01: Proceedings of the 38th annual Design Automation Conference

Pages 550 - 554

https://doi.org/10.1145/378239.379021

Published: 22 June 2001 Publication History

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Abstract

This paper presents an efficient algorithm for optimizing the area of power or ground networks in integrated circuits subject to the reliability constraints. Instead of solving the original power/ground networks extracted from circuit layouts as previous methods did, the new method first builds the equivalent models for many series resistors in the original networks, then the sequence of linear programming method [9] is used to solve the simplified networks. The solutions of the original networks then are back solved from the optimized, simplified networks. The new algorithm simply exploits the regularities in the power/ground networks. Experimental results show that the complexities of simplified networks are typically significantly smaller than that of the original circuits, which renders the new algorithm extremely fast. For instance, power/ground networks with more than one million branches can be sized in a few minutes on modern SUN workstations.

References

[1]

J. R. Black, "Electromigration failure modes in aluminum metalization for semiconductor devices," in Proc. of IEEE, vol. 57, pp.1587-1597, Sept. 1996.

Crossref

Google Scholar

[2]

S. Chowdhury and M. A. Breuer, "Minimal area design of power/ground nets having graph topologies," IEEE Trans. Circuits and Systems, vol. CAS-34, no. 12, pp. 1441-1451, Dec. 1987.

Google Scholar

[3]

S. Chowdhury and M. A. Breuer, "Optimum design of IC power/ground networks subject to reliability constraints," IEEE Trans. Computer-Aided Design, vol. 7, no. 7, pp. 787-796, July 1988.

Digital Library

Google Scholar

[4]

S. Chowdhury, "Optimum design of reliable IC power networks having general graph topologies," in Proc. 26th ACM/IEEE Design Automation Conf., pp. 787-790, 1989.

Digital Library

Google Scholar

[5]

R. Dutta and M. Marek-Sadowska, " Automatic sizing of power/ground (P/G) networks VLSI," in Proc. 26th ACM/IEEE Design Automation Conf., pp. 783-786, 1989.

Digital Library

Google Scholar

[6]

R. E. Griffith and R. A. Stewart, "A nonlinear programming technique for the optimization of continuous process systems," Management Science, no. 7, pp. 379-392, 1961.

Digital Library

Google Scholar

[7]

D. Stark and M. Horowitz, "Techniques for Calculating Currents and Voltages in VLSI Power Supply Networks," IEEE Trans. on Computer-Aided Design, vol. 9, no. 2, pp. 126-132, February 1990.

Digital Library

Google Scholar

[8]

H. Su, K. H. Gala and S. Sapatnekar, "Fast analysis and optimization of power/ground networks," in Proc. IEEE/ACM International Conf. on Computer-Aided Design., pp. 477-480, 2000.

Digital Library

Google Scholar

[9]

X.-D. Tan and C.-J. Richard Shi, "Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programming," in Proc. 36th ACM/IEEE Design Automation Conf., pp. 78-83, 1999.

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DAC '01: Proceedings of the 38th annual Design Automation Conference

June 2001

863 pages

ISBN:1581132972

DOI:10.1145/378239

Chairman:
Jan Rabaey
Univ. of California

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 22 June 2001

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Zhuo CLuo SGan HHu JShi Z(2019)Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT DevicesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.2917844(1-1)Online publication date: 2019
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Zhuo CUnda KShi YShih W(2019)From Layout to System: Early Stage Power Delivery and Architecture Co-ExplorationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283443838:7(1291-1304)Online publication date: Jul-2019
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Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling

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Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling

Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling

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