research-article

Optimal Allocation of LDOs and Decoupling Capacitors within a Distributed On-Chip Power Grid

Authors:

Sayed Abdullah Sadat,

Mustafa Canbolat,

Selçuk KöseAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 23, Issue 4

Article No.: 49, Pages 1 - 15

https://doi.org/10.1145/3177877

Published: 09 May 2018 Publication History

Abstract

Parallel on-chip voltage regulation, where multiple regulators are connected to the same power grid, has recently attracted significant attention with the proliferation of small on-chip voltage regulators. In this article, the number, size, and location of parallel low-dropout (LDO) regulators and intentional decoupling capacitors are optimized using mixed integer non-linear programming formulation. The proposed optimization function concurrently considers multiple objectives such as area, power noise, and overall power consumption. Certain objectives are optimized by putting constraints on the other objectives with the proposed technique. Additional constraints have been added to avoid the overlap of LDOs and decoupling capacitors in the optimization process. The results of an optimized LDO allocation in the POWER8 chip is compared with the recent LDO allocation in the same IBM chip in a case study where a 20% reduction in the noise is achieved. The results of the proposed multi-criteria objective function under a different area, power, and noise constraints are also evaluated with a sample ISPD’11 benchmark circuits in another case study.

References

[1]

C. Bienia, S. Kumar, J. P. Singh, and K. Li. 2008. The PARSEC benchmark suite: Characterization and architectural implications. In Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques (PACT’08). ACM, New York, NY, 72--81.

Digital Library

[2]

A. Brooke, D. Kendrick, A. Meeraus, and R. Raman. 1998. GAMS: A USER’S GUIDE. GAMS Development Corporation.

[3]

E. Chiprout. 2004. Fast flip-chip power grid analysis via locality and grid shells. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD’98). 485--488.

Digital Library

[4]

M. S. Daskin. 1995. Network and Discrete Location: Models, Algorithms, and Applications. John Wiley 8 Sons.

[5]

Z. Drezner and H. Hamacher. 2002. Facility Location. Springer.

[6]

R. Z. Farahani, M. SteadieSeifi, and N. Asgari. 2010. Multiple criteria facility location problems: A survey. Appl. Math. Model. 34, 7 (2010), 1689--1709.

[7]

E. J. Fluhr, J. Friedrich, D. Dreps, V. Zyuban, G. Still, C. Gonzalez, A. Hall, D. Hogenmiller, F. Malgioglio, R. Nett, J. Paredes, J. Pille, D. Plass, R. Puri, P. Restle, D. Shan, K. Stawiasz, Z. T. Deniz, D. Wendel, and M. Ziegler. 2014. POWER8: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. In Proceedings of the 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC’14). 96--97.

[8]

J. Guo and K. N. Leung. 2010. A 6-u W chip-area-efficient output-capacitorless LDO in 90-nm CMOS technology. IEEE J. Solid-State Circ. 45, 9 (Sep. 2010), 1896--1905.

[9]

P. Hazucha, T. Karnik, B. A. Bloechel, C. Parsons, D. Finan, and S. Borkar. 2005. Area-efficient linear regulator with ultra-fast load regulation. IEEE J. Solid-State Circ. 40, 4 (Apr. 2005), 933--940.

[10]

T. Karnik, M. Pant, and S. Borkar. 2013. Power management and delivery for high-performance microprocessors. In Proceedings of the International IEEE/ACM Design Automation Conference (DAC’13). 1--3.

Digital Library

[11]

S. K. Khatamifard, L. Wang, W. Yu, S. Köse, and U. R. Karpuzcu. 2017. ThermoGater: Thermally-aware on-chip voltage regulation. In Proceedings of the IEEE International Symposium on Computer Architecture (ISCA’17). 120--132.

Digital Library

[12]

S. Köse and E. G. Friedman. 2010a. An area efficient fully monolithic hybrid voltage regulator. In Proceedings of 2010 IEEE International Symposium on Circuits and Systems. 2718--2721.

[13]

S. Köse and E. G. Friedman. 2010b. Simultaneous co-design of distributed on-chip power supplies and decoupling capacitors. In Proceedings of the IEEE International System-on-Chip Conference (SoC’10).

[14]

S. Köse and E. G. Friedman. 2011a. Distributed power network co-design with on-chip power supplies and decoupling capacitors. In Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP’11).

Digital Library

[15]

S. Köse and E. G. Friedman. 2011b. Effective resistance of a two layer mesh. IEEE Trans. Circ. Syst. II 58, 11 (Nov. 2011), 739--743.

[16]

S. Köse and E. G. Friedman. 2012. Distributed on-chip power delivery. IEEE J. Emerg. Select. Top. Circ. Syst. 2, 4 (Dec. 2012), 704--713.

[17]

S. Köse, S. Tam, B. McDermott, and E. G. Friedman. 2013. Active filter based hybrid on-chip DC-DC converters for point-of-load voltage regulation. IEEE Trans. VLSI Syst. 21, 4 (Apr. 2013), 680--691.

Digital Library

[18]

N. Kurd, M. Chowdhury, E. Burton, T. P. Thomas, C. Mozak, B. Boswell, M. Lal, A. Deval, J. Douglas, M. Elassal, A. Nalamalpu, T. M. Wilson, M. Merten, S. Chennupaty, W. Gomes, and R. Kumar. 2014. Haswell: A family of IA 22nm processors. In Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC’14). 112--113.

[19]

S. Lai and P. Li. 2012. A fully on-chip area-efficient CMOS low-dropout regulator with fast load regulation. Analog Integr. Circ. Sign. Process. 72, 2 (2012), 433--450.

Digital Library

[20]

S. Lai, B. Yan, and P. Li. 2013. Localized stability checking and design of IC power delivery with distributed voltage regulators. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 32, 9 (Sep. 2013), 1321--1334.

Digital Library

[21]

Ka Nang Leung and P. K. T. Mok. 2003. A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation. IEEE J. Solid-State Circ. 38, 10 (Oct 2003), 1691--1702.

[22]

H. Li, X. Wang, J. Xu, Z. Wang, R. K. V. Maeda, Z. Wang, P. Yang, L. H. K. Duong, and Z. Wang. 2017. Energy-efficient power delivery system paradigms for many-core processors. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 36, 3 (Mar. 2017), 449--462.

Digital Library

[23]

M. D. Pant, P. Pant, and D. S. Wills. 2002. On-chip decoupling capacitor optimization using architectural level prediction. IEEE Trans. VLSI Syst. 10, 3 (Jun. 2002), 319--326.

Digital Library

[24]

M. Popovich, E. G. Friedman, R. M. Secareanu, and O. L. Hartin. 2007. Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs. In Proceedings of the 2007 IEEE/ACM International Conference on Computer-Aided Design. 811--816.

Digital Library

[25]

Y. K. Ramadass, A. A. Fayed, and A. P. Chandrakasan. 2010. A fully-integrated switched-capacitor step-down DC-DC converter with digital capacitance modulation in 45nm CMOS. IEEE J. Solid-State Circ. 45, 12 (Dec. 2010), 2557--2565.

[26]

S. R. Sanders, E. Alon, H. P. Le, M. D. Seeman, M. John, and V. W. Ng. 2013. The road to fully integrated DC-DC conversion via the switched-capacitor approach. IEEE Trans. Power Electron. 28, 9 (Sep. 2013), 4146--4155.

[27]

X. D. S. Tan and C. J. R. Shi. 2001. Fast power/ground network optimization based on equivalent circuit modeling. In Proceedings of the 38th Design Automation Conference. 550--554.

Digital Library

[28]

M. K. Tavana, M. H. Hajkazemi, D. Pathak, I. Savidis, and H. Homayoun. 2015. ElasticCore: Enabling dynamic heterogeneity with joint core and voltage/frequency scaling. In Proceedings of the 52nd Annual Design Automation Conference (DAC’15). ACM, New York, NY, Article 151, 6 pages.

Digital Library

[29]

Z. Toprak-Deniz, M. Sperling, J. Bulzacchelli, G. Still, R. Kruse, S. Kim, D. Boerstler, T. Gloekler, R. Robertazzi, K. Stawiasz, T. Diemoz, G. English, D. Hui, P. Muench, and J. Friedrich. 2014. Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8 microprocessor. In Proceedings of the 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC’14). 98--99.

[30]

I. Vaisband and E. G. Friedman. 2016. Stability of distributed power delivery systems with multiple parallel on-chip LDO regulators. IEEE Trans. Power Electron. 31, 8 (Aug. 2016), 5625--5634.

[31]

I. Vaisband, R. Jakushokas, M. Popovich, A. V. Mezhiba, S. Köse, and E. G. Friedman. 2016. In On-Chip Power Delivery and Management.

[32]

N. Viswanathan, C. J. Alpert, C. Sze, Z. Li, G.-J. Nam, and J. A. Roy. 2011. The ISPD-2011 routability-driven placement contest and benchmark suite. In Proceedings of the International Symposium on Physical Design (ISPD’11). ACM, New York, NY, 141--146.

Digital Library

[33]

K. Wang and M. Marek-Sadowska. 2005. On-chip power-supply network optimization using multigrid-based technique. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 24, 3 (Mar. 2005), 407--417.

Digital Library

[34]

L. Wang, S. K. Khatamifard, U. R. Karpuzcu, and S. Köse. 2018. Mitigation of NBTI induced performance degradation in on-chip digital LDOs. In Proceedings of the IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE’18).

[35]

L. Wang, S. K. Khatamifard, O. A. Uzun, U. R. Karpuzcu, and S. Köse. 2017. Efficiency, stability, and reliability implications of unbalanced current sharing among distributed on-chip voltage regulators. IEEE Trans. VLSI Syst. 25, 11 (Nov. 2017), 3019--3032.

[36]

T. Yu and M. D. F. Wong. 2014. Efficient simulation-based optimization of power grid with on-chip voltage regulator. In Proceedings of the 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC’14). 531--536.

[37]

Z. Zeng, S. Lai, and P. Li. 2013. IC power delivery: Voltage regulation and conversion, system-level cooptimization and technology implications. ACM Trans. Des. Autom. Electron. Syst. 18, 2, Article 29 (April 2013), 21 pages.

Digital Library

[38]

Z. Zeng, X. Ye, Z. Feng, and P. Li. 2010. Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation. In Proceedings of the Design Automation Conference. 831--836.

Digital Library

[39]

X. Zhan, P. Li, and E. Sanchez-Sinencio. 2016. Distributed on-chip regulation: Theoretical stability foundation, over-design reduction and performance optimization. In Proceedings of the 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC’16). 1--6.

Digital Library

[40]

R. Zhang, K. Mazumdar, B. H. Meyer, K. Wang, K. Skadron, and M. R. Stan. 2015. Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC. In Proceedings of the 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED’15). 152--158.

[41]

P. Zhou, A. Paul, C. H. Kim, and S. S. Sapatnekar. 2014. Distributed on-chip switched-capacitor DC-DC converters supporting DVFS in multicore systems. IEEE Trans. VLSI Syst. 22, 9 (Sep. 2014), 1954--1967.

Cited By

Bairamkulov RFriedman E(2024)Power Aware Placement of On-Chip Voltage RegulatorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.331928543:2(654-666)Online publication date: 1-Feb-2024
https://dl.acm.org/doi/10.1109/TCAD.2023.3319285
Dey SNandi STrivedi G(2020)PGOpt: Multi-objective Design Space Exploration Framework for Large-Scale On-Chip Power Grid Design in VLSI SoC using Evolutionary Computing TechniqueMicroprocessors and Microsystems10.1016/j.micpro.2020.103440(103440)Online publication date: Nov-2020
https://doi.org/10.1016/j.micpro.2020.103440

Index Terms

Optimal Allocation of LDOs and Decoupling Capacitors within a Distributed On-Chip Power Grid
1. Hardware
  1. Power and energy
    1. Power estimation and optimization
      1. Chip-level power issues
      2. Circuits power issues
  2. Very large scale integration design

Recommendations

Effective radii of on-chip decoupling capacitors

Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on a die or placed inside the rows in standard ceil circuit blocks. The efficacy of on-...
Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs
ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on the die based on an unsystematic or ad hoc approach. In this way, large decoupling ...
Maximum effective distance of on-chip decoupling capacitors in power distribution grids
GLSVLSI '06: Proceedings of the 16th ACM Great Lakes symposium on VLSI

Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the available white space on a die. The efficacy of on-chip decoupling capacitors depends upon the impedance of the ...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 23, Issue 4

Special Section on Advances in Physical Design Automation and Regular Papers

July 2018

316 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3217208

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

Issue’s Table of Contents

Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 09 May 2018

Accepted: 01 January 2018

Revised: 01 December 2017

Received: 01 May 2017

Published in TODAES Volume 23, Issue 4

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Funding Sources

National Science Foundation CAREER Award
Cisco Research Award

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
137
Total Downloads

Downloads (Last 12 months)10
Downloads (Last 6 weeks)2

Reflects downloads up to 13 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

Bairamkulov RFriedman E(2024)Power Aware Placement of On-Chip Voltage RegulatorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.331928543:2(654-666)Online publication date: 1-Feb-2024
https://dl.acm.org/doi/10.1109/TCAD.2023.3319285
Dey SNandi STrivedi G(2020)PGOpt: Multi-objective Design Space Exploration Framework for Large-Scale On-Chip Power Grid Design in VLSI SoC using Evolutionary Computing TechniqueMicroprocessors and Microsystems10.1016/j.micpro.2020.103440(103440)Online publication date: Nov-2020
https://doi.org/10.1016/j.micpro.2020.103440

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Issue’s Table of Contents