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A new structural pattern matching algorithm for technology mapping

Authors:

Min Zhao,

Sachin S. SapatnekarAuthors Info & Claims

DAC '01: Proceedings of the 38th annual Design Automation Conference

Pages 371 - 376

https://doi.org/10.1145/378239.378526

Published: 22 June 2001 Publication History

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Abstract

In this paper, a new structural matching algorithm for technology mapping is proposed. The algorithm is based on a key observation that the matches for a node in a subject Boolean network are related to the matches for its children. The structural relationships between the library cells are modeled using a lookup table. The proposed method is fast, has low memory usage, and is easy to implement. Experimental results show speedups of 20x over Matsunaga's fast mapping approach, and orders of magnitude over SIS, with the same or slightly better results, and much lower memory utilization.

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Feng LSha JWang Z(2023)1+1 <2: Efficient Automatic Standard Cell Sharing Between Digital VLSI Designs for Area SavingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.324488942:11(4177-4190)Online publication date: Nov-2023
https://doi.org/10.1109/TCAD.2023.3244889
Vemuri RChen SVemuri RChen S(2021)Design Constraint Based AttacksSplit Manufacturing of Integrated Circuits for Hardware Security and Trust10.1007/978-3-030-73445-9_2(31-62)Online publication date: 13-Mar-2021
https://doi.org/10.1007/978-3-030-73445-9_2
Xu WFeng LRajendran JHu JShibuya T(2019)Layout recognition attacks on split manufacturingProceedings of the 24th Asia and South Pacific Design Automation Conference10.1145/3287624.3287698(45-50)Online publication date: 21-Jan-2019
https://dl.acm.org/doi/10.1145/3287624.3287698
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A new structural pattern matching algorithm for technology mapping

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DAC '01: Proceedings of the 38th annual Design Automation Conference

June 2001

863 pages

ISBN:1581132972

DOI:10.1145/378239

Chairman:
Jan Rabaey
Univ. of California

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 22 June 2001

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Feng LSha JWang Z(2023)1+1 <2: Efficient Automatic Standard Cell Sharing Between Digital VLSI Designs for Area SavingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.324488942:11(4177-4190)Online publication date: Nov-2023
https://doi.org/10.1109/TCAD.2023.3244889
Vemuri RChen SVemuri RChen S(2021)Design Constraint Based AttacksSplit Manufacturing of Integrated Circuits for Hardware Security and Trust10.1007/978-3-030-73445-9_2(31-62)Online publication date: 13-Mar-2021
https://doi.org/10.1007/978-3-030-73445-9_2
Xu WFeng LRajendran JHu JShibuya T(2019)Layout recognition attacks on split manufacturingProceedings of the 24th Asia and South Pacific Design Automation Conference10.1145/3287624.3287698(45-50)Online publication date: 21-Jan-2019
https://dl.acm.org/doi/10.1145/3287624.3287698
Folco BBrégier VFesquet LRenaudin M(2007)Technology Mapping for Area Optimized Quasi Delay Insensitive CircuitsVlsi-Soc: From Systems To Silicon10.1007/978-0-387-73661-7_5(55-69)Online publication date: 2007
https://doi.org/10.1007/978-0-387-73661-7_5
Cserkuti PLevendovszky TCharaf H(2006)Survey on Subtree Matching2006 International Conference on Intelligent Engineering Systems10.1109/INES.2006.1689372(216-221)Online publication date: 2006
https://doi.org/10.1109/INES.2006.1689372
Correia VReis ANatividade da Silva Barros EWagner FCarro LRammig F(2004)Advanced technology mapping for standard-cell generatorsProceedings of the 17th symposium on Integrated circuits and system design10.1145/1016568.1016636(254-259)Online publication date: 4-Sep-2004
https://dl.acm.org/doi/10.1145/1016568.1016636

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A new regular grammar pattern matching algorithm

In-Depth Packet Inspection Using a Hierarchical Pattern Matching Algorithm

Multi-pattern Matching Algorithm based on Variable Step Size

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