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Carbon nanotube computer

Nature volume 501, pages 526–530 (2013)Cite this article

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Abstract

The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy–delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies1,2. Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems3,4.

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Figure 1: SUBNEG and program implementation.
Figure 2: Schematic of CNT computer.
Figure 3: Characterization of CNFET subcomponents.
Figure 4: CNT computer results.

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References

  1. Franklin, A. D. et al. Sub-10 nm carbon nanotube transistor. Nano Lett. 12, 758–762 (2012)

    Article  CAS  ADS  Google Scholar 

  2. Wei, L., Frank, D., Chang, L. & Wong, H.-S. P. in Proc. 2009 IEEE Intl Electron Devices Meeting 917–920 (IEEE, 2009)

    Google Scholar 

  3. Chang, L. in Short Course IEEE Intl Electron Devices Meeting (IEEE, 2012)

    Google Scholar 

  4. Nikonov, D. & Young, I. in Proc. 2012 IEEE Intl Electron Devices Meeting 24–25 (IEEE, 2012)

    Google Scholar 

  5. Javey, A., Guo, J., Wang, Q., Lundstrom, M. & Dai, H. Ballistic carbon nanotube transistors. Nature 424, 654–657 (2003)

    Article  CAS  ADS  Google Scholar 

  6. Javey, A., Wang, Q., Kim, W. & Dai, H. in 2003 Intl Electron Devices Meeting Tech. Digest 31–32 (IEEE, 2003)

    Google Scholar 

  7. Appenzeller, J. Carbon nanotubes for high-performance electronics—progress and prospect. Proc. IEEE 96, 201–211 (2008)

    Article  CAS  Google Scholar 

  8. Deng, J. et al. in Proc. 2007 IEEE Intl Solid State Circuits Conf. 70–78 (IEEE, 2007)

  9. Iijima, S. Helical microtubules of graphitic carbon. Nature 354, 56–58 (1991)

    Article  CAS  ADS  Google Scholar 

  10. Martel, R. A. ., Schmidt, T., Shea, H. R., Hertel, T. & Avouris, P. Single-and multi-wall carbon nanotube field-effect transistors. Appl. Phys. Lett. 73, 2447 (1998)

    Article  CAS  ADS  Google Scholar 

  11. Tans, S. J., Verschueren, A. R. & Dekker, C. Room-temperature transistor based on a single carbon nanotube. Nature 393, 49–52 (1998)

    Article  CAS  ADS  Google Scholar 

  12. Chen, Z. et al. An integrated logic circuit assembled on a single carbon nanotube. Science 311, 1735 (2006)

    Article  CAS  Google Scholar 

  13. Cao, Q. et al. Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates. Nature 454, 495–500 (2008)

    Article  CAS  ADS  Google Scholar 

  14. Patil, N., Lin, A., Myers, E. R., Wong, H.-S. P. & Mitra, S. in Proc. Symp. VLSI Tech. 205–206. (2008)

  15. Patil, N. et al. Scalable carbon nanotube computational and storage circuits immune to metallic and mis-positioned carbon nanotubes. IEEE Trans. NanoTechnol. 10, 744–750 (2011)

    Article  ADS  Google Scholar 

  16. Shulaker, M. et al. in Proc. 2013 IEEE Intl Solid State Circuits Conf. 112–113 (IEEE, 2013)

  17. von Neumann, J. First draft of a report on the EDVAC. Ann. Hist. Comput. 15, 27–75 (1993)

    Article  MathSciNet  Google Scholar 

  18. McCluskey, E. J. Logic Design Principles with Emphasis on Testable Semicustom Circuits (Prentice-Hall, 1986)

    Google Scholar 

  19. Cao, Q. et al. Arrays of single-walled carbon nanotubes with full surface coverage for high-performance electronics. Nature Nanotechnol. 8, 180–186 (2013)

    Article  CAS  ADS  Google Scholar 

  20. Zhang, J. et al. Robust digital VLSI using carbon nanotubes. IEEE Trans. CAD 31, 453–471 (2012)

    Article  CAS  Google Scholar 

  21. Patil, N. Design and Fabrication of Imperfection-Immune Carbon Nanotube Digital VLSI Circuits. PhD thesis, Stanford Univ. (2010)

  22. Patterson, D. A. & Hennessy, J. L. Computer Architecture (Kaufmann, 1990)

    MATH  Google Scholar 

  23. Lin, A. Carbon Nanotube Synthesis, Device Fabrication, and Circuit Design for Digital Logic Applications. PhD thesis, Stanford Univ. (2010)

  24. Herken, R., ed. The Universal Turing Machine: A Half-Century Survey (Springer, 1995)

  25. Nürnberg, P., Uffe, W. & Hicks, D. A grand unified theory for structural computing. Metainformatics 3002, 1–16 (2004)

    Article  Google Scholar 

  26. Jeffay, K., Donald, S. F. & Martel, C. U. in Proc. Real-Time Systems Symposium 129–139 (IEEE, 1991)

    Google Scholar 

  27. Shulaker, M. et al. Linear increases in carbon nanotube density through multiple transfer technique. Nano Lett. 11, 1881–1886 (2011)

    Article  CAS  ADS  Google Scholar 

  28. Bachtold, A., Hadley, P., Nakanishi, T. & Dekker, C. Logic circuits with carbon nanotube transistors. Science 294, 1317–1320 (2001)

    Article  CAS  ADS  Google Scholar 

  29. Collins, P. G., Arnold, M. S. & Avouris, P. Engineering carbon nanotubes and nanotube circuits using electrical breakdown. Science 292, 706–709 (2001)

    Article  CAS  ADS  Google Scholar 

  30. Patil, N. et al. in Proc. 2009 IEEE Intl Electron Devices Meeting 573–576 (IEEE, 2009)

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Acknowledgements

We acknowledge the support of the NSF (CISE) (CNS-1059020, CCF-0726791, CCF-0702343, CCF-0643319), FCRP C2S2, FCRP FENA, STARNet SONIC and the Stanford Graduate Fellowship and the Hertz Foundation Fellowship (M.M.S.). We also acknowledge Z. Bao, A. Lin, H. (D.) Lin, M. Rosenblum, and J. Zhang for their advice and collaborations.

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Authors and Affiliations

  1. Stanford University, Gates Building, Room 331, 353 Serra Mall, Stanford, California 94305, USA,

    Max M. Shulaker

  2. Stanford University, Gates Building, Room 358, 353 Serra Mall, Stanford, California 94305, USA,

    Gage Hills

  3. SK Hynix Memory Solutions, 3103 North First Street, San Jose, 95134, California, USA

    Nishant Patil

  4. Stanford University, Gates Building, Room 239, 353 Serra Mall, Stanford, California 94305, USA,

    Hai Wei

  5. Stanford University, Paul G. Allen Building, Room B113X, 420 Via Ortega, Stanford, California 94305, USA,

    Hong-Yu Chen

  6. Stanford University, Paul G. Allen Building, Room 312X, 420 Via Ortega, Stanford, California 94305, USA,

    H.-S. Philip Wong

  7. Stanford University, Gates Building, Room 334, 353 Serra Mall, Stanford, California 94305, USA,

    Subhasish Mitra

Authors
  1. Max M. Shulaker
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  7. Subhasish Mitra
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Contributions

M.M.S. led and was involved in all aspects of the project, did all of the fabrication and layout designs, and contributed to the design and testing. G.H. wrote the SUBNEG and testing programs, and contributed to the design and testing. N.P. contributed to the design, and N.P., H.W. and H.-Y.C. contributed to developing fabrication processes. H.-S.P.W. and S.M. were in charge and advised on all parts of the project.

Corresponding author

Correspondence to Max M. Shulaker.

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Competing interests

The authors declare no competing financial interests.

Extended data figures and tables

Extended Data Figure 1 Fabrication flow for the CNT computer.

Steps 1–4 prepare the final substrate for circuit fabrication. Steps 5–8 transfer the CNTs from the quartz wafer (where highly aligned CNTs are grown) to the final SiO2 substrate. Steps 9–11 continue final device fabrication on the final substrate.

Extended Data Figure 2 Multibit arithmetic unit.

a, Schematic of a two-bit arithmetic unit, comprising six individual arithmetic logic units (ALU) as shown in Fig. 3b. b, Measured and expected output waveforms testing all possible input combinations of the two-bit arithmetic unit, showing correct operation.

Extended Data Figure 3 Internal versus external connections of CNT computer.

a, Schematic of the CNT computer, showing that all connections are fabricated on-chip and that only signals reading or writing to or from an external memory are connected off-chip. b, SEM of the CNT computer, showing which connections are made to and from the CNT computer from the probe pads. The SEM is colour-coded to match the coloured wires in a.

Extended Data Figure 4 PMOS-only logic schematics.

a, Schematic of PMOS-only inverter. b, Schematic of PMOS-only NAND gate.

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Shulaker, M., Hills, G., Patil, N. et al. Carbon nanotube computer. Nature 501, 526–530 (2013). https://doi.org/10.1038/nature12502

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