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Improved clock-gating through transparent pipelining

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Hans M. JacobsonAuthors Info & Claims

ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design

Pages 26 - 31

https://doi.org/10.1145/1013235.1013248

Published: 09 August 2004 Publication History

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Abstract

This paper re-examines the well established clocking principles of pipelines. It is observed that clock gating techniques that have long been assumed optimal in reality produce a significant amount of redundant clock pulses. The paper presents a new theory for optimal clocking of synchronous pipelines, presents practical implementations and evaluates the clock power benefits on a multiply/add-accumulate unit design. Transistor level simulations show that dynamic clock power dissipation can be reduced by 40-60% at pipeline utilization factors between 20-60%, on top of traditional stage-level clock gating, without affecting pipeline latency or throughput.

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Hameed AAkawee MHameed M(2022)Power Reduction using Pipeline-Clock Gating Technique in Synchronous Design with FPGA Implementation2022 3rd Information Technology To Enhance e-learning and Other Application (IT-ELA)10.1109/IT-ELA57378.2022.10107932(210-214)Online publication date: 27-Dec-2022
https://doi.org/10.1109/IT-ELA57378.2022.10107932
Jain SLin LAlioto M(2020)Automated Design of Reconfigurable Microarchitectures for Accelerators Under Wide-Voltage ScalingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.295095928:3(777-790)Online publication date: Mar-2020
https://doi.org/10.1109/TVLSI.2019.2950959
Jain SLin LAlioto MJain SLin LAlioto M(2020)Automated Design Flows and Run-Time Optimization for Reconfigurable MicroarchitecuresAdaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling10.1007/978-3-030-38796-9_3(55-92)Online publication date: 28-Feb-2020
https://doi.org/10.1007/978-3-030-38796-9_3
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Index Terms

Improved clock-gating through transparent pipelining
1. Computer systems organization
  1. Architectures
    1. Serial architectures
      1. Pipeline computing

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Published In

ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design

August 2004

414 pages

ISBN:1581139292

DOI:10.1145/1013235

General Chairs:
Rajiv Joshi
IBM
,
Kiyoung Choi
Seoul National University
,
Program Chairs:
Vivek Tiwari
Intel Corporation
,
Kaushik Roy
Purdue University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 09 August 2004

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ISLPED04: International Symposium on Low Power Electronics and Design

August 9 - 11, 2004

California, Newport Beach, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Hameed AAkawee MHameed M(2022)Power Reduction using Pipeline-Clock Gating Technique in Synchronous Design with FPGA Implementation2022 3rd Information Technology To Enhance e-learning and Other Application (IT-ELA)10.1109/IT-ELA57378.2022.10107932(210-214)Online publication date: 27-Dec-2022
https://doi.org/10.1109/IT-ELA57378.2022.10107932
Jain SLin LAlioto M(2020)Automated Design of Reconfigurable Microarchitectures for Accelerators Under Wide-Voltage ScalingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.295095928:3(777-790)Online publication date: Mar-2020
https://doi.org/10.1109/TVLSI.2019.2950959
Jain SLin LAlioto MJain SLin LAlioto M(2020)Automated Design Flows and Run-Time Optimization for Reconfigurable MicroarchitecuresAdaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling10.1007/978-3-030-38796-9_3(55-92)Online publication date: 28-Feb-2020
https://doi.org/10.1007/978-3-030-38796-9_3
Jain SLin LAlioto MJain SLin LAlioto M(2020)Reconfigurable Microarchitecures Down to Pipestage and Memory Bank LevelAdaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling10.1007/978-3-030-38796-9_2(17-53)Online publication date: 28-Feb-2020
https://doi.org/10.1007/978-3-030-38796-9_2
Ravi GLipasti M(2018)Aggressive Slack Recycling via Transparent PipelinesProceedings of the International Symposium on Low Power Electronics and Design10.1145/3218603.3218623(1-6)Online publication date: 23-Jul-2018
https://dl.acm.org/doi/10.1145/3218603.3218623
Jain SLin LAlioto M(2018)Dynamically Adaptable Pipeline for Energy-Efficient Microarchitectures Under Wide Voltage ScalingIEEE Journal of Solid-State Circuits10.1109/JSSC.2017.276840653:2(632-641)Online publication date: Feb-2018
https://doi.org/10.1109/JSSC.2017.2768406
Manikanth KRamesh S(2018)Design of Soft Edge Flip Flops for the Reduction of Power Delay Product in Linear Pipeline Circuits2018 International Conference on Communication and Signal Processing (ICCSP)10.1109/ICCSP.2018.8524364(0148-0151)Online publication date: Apr-2018
https://doi.org/10.1109/ICCSP.2018.8524364
Ravi GLipasti M(2017)Timing Speculation in Multi-Cycle Data PathsIEEE Computer Architecture Letters10.1109/LCA.2016.258050116:1(84-87)Online publication date: 1-Jan-2017
https://doi.org/10.1109/LCA.2016.2580501
Gopireddy BSong CTorrellas JKim NAgrawal AMishra A(2016)ScalCore: Designing a core for voltage scalability2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446104(681-693)Online publication date: Mar-2016
https://doi.org/10.1109/HPCA.2016.7446104
Chen RKuo X(2016)Design of a Transparent Pipeline-Based MultiplierProceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems (ICITES2014)10.1007/978-3-319-17314-6_62(485-491)Online publication date: 2016
https://doi.org/10.1007/978-3-319-17314-6_62
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Ultra low-power clocking scheme using energy recovery and clock gating

Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks

Clock Gating Aware Low Power Global Reset ALU and Implementation on 28nm FPGA

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Ultra low-power clocking scheme using energy recovery and clock gating

Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks

Clock Gating Aware Low Power Global Reset ALU and Implementation on 28nm FPGA

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