Article

Floorplan-aware automated synthesis of bus-based communication architectures

Authors:

Sudeep Pasricha,

Elaheh Bozorgzadeh,

Mohamed Ben-RomdhaneAuthors Info & Claims

DAC '05: Proceedings of the 42nd annual Design Automation Conference

Pages 565 - 570

https://doi.org/10.1145/1065579.1065727

Published: 13 June 2005 Publication History

Abstract

As System-on-Chip (SoC) designs become more complex, it is becoming harder to design communication architectures to handle the ever increasing volumes of inter-component communication. Manual traversal of the vast communication design space to synthesize a communication architecture that meets performance requirements becomes infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing cost-effective, bus-based communication architectures that satisfy the performance constraints in a design. Our synthesis flow also incorporates a high-level floorplanning and wire delay estimation engine to evaluate the feasibility of the synthesized bus architecture and detect timing violations early in the design flow. We present case studies of network communication SoC subsystems for which we synthesized bus architectures, detected timing violations and generated core placements in a matter of hours instead of several days it took for a manual effort.

References

[1]

D. Sylvester and K. Keutzer, "Getting to the bottom of deep sub-micron", In Proc. of ICCAD 1998

Digital Library

[2]

Flynn, "AMBA: enabling reusable on-chip designs" In IEEE Micro, 1997

Digital Library

[3]

IBM CoreConnect http://www.chips.ibm.com/products/powerpc/cores

[4]

Open Core Protocol International Partnership (OCP-IP). OCP datasheet, http://www.ocpip.org

[5]

S. Pasricha, N. Dutt, M. Ben-Romdhane, "Fast Exploration of Bus-based On-chip Communication Architectures", In Proc. of CODES-ISSS 2004

Digital Library

[6]

S. Narayan, D. Gajski, "Synthesis of system level bus interfaces", In Proc. of DATE 1994

[7]

J. Daveau, et al "Protocol selection and interface generation for HW-SW codesign", In IEEE Trans. on VLSI System, Vol. 5, No. 1, March 1997

Digital Library

[8]

M. Gasteier, M. Glesner "Bus-based communication synthesis on system level", In ACM TODAES, January 1999

Digital Library

[9]

K. K. Ryu, V. J. Mooney III "Automated Bus Generation for Multiprocessor SoC Design", In Proc. of DATE 2003

Digital Library

[10]

A. Pinto et al "Constraint-driven communication synthesis", DAC 2002

Digital Library

[11]

D. Lyonnard et al "Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip", DAC 2001

Digital Library

[12]

K. Lahiri et al, "Efficient exploration of the SoC communication architecture design space", In Proc. of ICCAD 2000

Digital Library

[13]

C. Shin, et al "Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design", In Proc. of DATE 2004

Digital Library

[14]

N. Thepayasuwan, A. Doboli "Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip", In Proc. of DATE 2004

Digital Library

[15]

M. Drinic et al. "Latency-guided on-chip bus network design", In Proc. of ICCAD 2000

Digital Library

[16]

J. Hu et al, "System-Level Point-to-Point Communication Synthesis Using Floorplanning Information", In Proc. of ASP-DAC 2002

Digital Library

[17]

R. P. Dick, N. K. Jha "MOCSYN: multiobjective core-based single-chip system synthesis", In Proc. of DATE 1999

Digital Library

[18]

R. A. Bergamaschi et al "SEAS: a system for early analysis of SoCs", In Proc. of CODES-ISSS 2003

Digital Library

[19]

S. N. Adya, I. L. Markov, "Fixed-outline Floorplanning: Enabling Hierarchical Design", In IEEE Trans TVLSI, Dec. 2003

Digital Library

[20]

A. E. Caldwell, et al, "On Wirelength Estimations for Row-based Placement", In IEEE Trans. on ICCAD, vol.18, (no.9), IEEE, Sept. 1999

Digital Library

[21]

J. Cong, D. Z. Pan, "Interconnect Performance Estimation Models for Design Planning", In IEEE Trans. on ICCAD, Vol 20, No. 6, June 2001

Digital Library

[22]

Semiconductor Industry Association, "National Technology Roadmap for Semiconductors", SIA 1997

[23]

SystemC initiative. www.systemc.org

[24]

S. Pasricha, "Transaction Level Modeling of SoC with SystemC 2.0", In Proc. of Synopsys User Group Conference (SNUG), 2002

[25]

AMBA AXI Specification www.arm.com/armtech/AXI

[26]

S. Pasricha, N. Dutt, M. Ben-Romdhane, "Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration", In Proc. of DAC 2004

Digital Library

Cited By

Chen WWang XSun YHu QHuang LJiang YSingh AMak TYang M(2021)Evolution of Publications, Subjects, and Co-Authorships in Network-on-Chip Research From a Complex Network PerspectiveIEEE Access10.1109/ACCESS.2021.31231069(149399-149422)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3123106
Cheng YYu TFang S(2020)Obstacle-Avoiding Length-Matching Bus Routing Considering Nonuniform Track ResourcesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.298531228:8(1881-1892)Online publication date: Aug-2020
https://doi.org/10.1109/TVLSI.2020.2985312
Eder JVoss SBayha AIpatiov AKhalil M(2020)Hardware architecture exploration: automatic exploration of distributed automotive hardware architecturesSoftware and Systems Modeling10.1007/s10270-020-00786-6Online publication date: 12-Mar-2020
https://doi.org/10.1007/s10270-020-00786-6
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Index Terms

Floorplan-aware automated synthesis of bus-based communication architectures
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design

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Published In

cover image ACM Conferences

DAC '05: Proceedings of the 42nd annual Design Automation Conference

June 2005

984 pages

ISBN:1595930582

DOI:10.1145/1065579

General Chair:
William H. Joyner
IBM Corp./SRC
,
Program Chairs:
Grant E. Martin
Tensilica, Inc.
,
Andrew B. Kahng
University of California at San Diego, CA

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 13 June 2005

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DAC05

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DAC05: The 42nd Annual Design Automation Conference 2005

June 13 - 17, 2005

California, Anaheim, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Chen WWang XSun YHu QHuang LJiang YSingh AMak TYang M(2021)Evolution of Publications, Subjects, and Co-Authorships in Network-on-Chip Research From a Complex Network PerspectiveIEEE Access10.1109/ACCESS.2021.31231069(149399-149422)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3123106
Cheng YYu TFang S(2020)Obstacle-Avoiding Length-Matching Bus Routing Considering Nonuniform Track ResourcesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.298531228:8(1881-1892)Online publication date: Aug-2020
https://doi.org/10.1109/TVLSI.2020.2985312
Eder JVoss SBayha AIpatiov AKhalil M(2020)Hardware architecture exploration: automatic exploration of distributed automotive hardware architecturesSoftware and Systems Modeling10.1007/s10270-020-00786-6Online publication date: 12-Mar-2020
https://doi.org/10.1007/s10270-020-00786-6
Liu DYu BLivramento VChowdhury SDing DVo HSharma APan D(2019)Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal GroupsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283442438:6(1147-1160)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1109/TCAD.2018.2834424
Eder J(2018)Exploration of hardware topologies based on functions, variability and timingProceedings of the 21st ACM/IEEE International Conference on Model Driven Engineering Languages and Systems: Companion Proceedings10.1145/3270112.3275333(145-149)Online publication date: 14-Oct-2018
https://dl.acm.org/doi/10.1145/3270112.3275333
Eder JBahya AVoss SIpatiov AKhalil MWąsowski APaige RHaugen Ø(2018)From Deployment to Platform ExplorationProceedings of the 21th ACM/IEEE International Conference on Model Driven Engineering Languages and Systems10.1145/3239372.3239385(438-446)Online publication date: 14-Oct-2018
https://dl.acm.org/doi/10.1145/3239372.3239385
Liu DLivramento VChowdhury SDing DVo HSharma APan D(2017)StreakProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062321(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062321
Kwon WPeh LMarculescu DLiu F(2015)A universal ordered NoC design platform for shared-memory MPSoCProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840916(697-704)Online publication date: 2-Nov-2015
https://dl.acm.org/doi/10.5555/2840819.2840916
Lee JChung MCho YRyu SAhn JChoi K(2013)Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory ConstraintIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.226640532:11(1748-1761)Online publication date: 1-Nov-2013
https://dl.acm.org/doi/10.1109/TCAD.2013.2266405
Sombatsiri SKobashi KSakanushi KTakeuchi YImai M(2013)An AMBA hierarchical shared bus architecture design space exploration method considering pipeline, burst and split transaction2013 10th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology10.1109/ECTICon.2013.6559529(1-6)Online publication date: May-2013
https://doi.org/10.1109/ECTICon.2013.6559529
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