Article

CMP aware shuttle mask floorplanning

Authors:

Gang Xu,

Ruiqi Tian,

David Z. Pan,

Martin D. F. WongAuthors Info & Claims

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Pages 1111 - 1114

https://doi.org/10.1145/1120725.1120836

Published: 18 January 2005 Publication History

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Abstract

By putting different chips on the same mask, shuttle mask (or multiple project wafer) provides an economical solution for low volume designs and design prototypes to share the rising mask cost. A challenging floorplanning problem is to optimally pack these chips according to objectives and constraints related to cost and manufacturability. In this paper, we study the problem of CMP aware shuttle mask floorplanning, which is formulated as a rectangle packing problem with objectives of area and post-CMP topography variation minimization. We propose a 3-step procedure to solve the problem. First, we use the low-pass filter oxide CMP model to guide the simulated annealing search to minimize the topography variation. The result is then further improved by sliding each chip in its enclosing rectangle. Finally, we calculate the optimal amount of dummy feature needed with a linear programming method. Our experiment show excellent results on real industry data.

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Cited By

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Nisted LPisinger DAltman A(2011)Optimal wafer cutting in shuttle layout problemsJournal of Combinatorial Optimization10.1007/s10878-009-9284-z22:2(202-216)Online publication date: 1-Aug-2011
https://dl.acm.org/doi/10.1007/s10878-009-9284-z
Cho MLu KYuan KPan D(2009)BoxRouter 2.0ACM Transactions on Design Automation of Electronic Systems10.1145/1497561.149757514:2(1-21)Online publication date: 7-Apr-2009
https://dl.acm.org/doi/10.1145/1497561.1497575
Wu MLin RTsai S(2008)Chip placement in a reticle for multiple-project wafer fabricationACM Transactions on Design Automation of Electronic Systems10.1145/1297666.129768813:1(1-21)Online publication date: 6-Feb-2008
https://dl.acm.org/doi/10.1145/1297666.1297688

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ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

January 2005

1495 pages

ISBN:0780387376

DOI:10.1145/1120725

General Chair:
Ting-Ao Tang
Fudan University, Shanghai, P. R. China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 18 January 2005

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ASPDAC05: Asia and South Pacific Design Automation Conference

January 18 - 21, 2005

Shanghai, China

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

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Nisted LPisinger DAltman A(2011)Optimal wafer cutting in shuttle layout problemsJournal of Combinatorial Optimization10.1007/s10878-009-9284-z22:2(202-216)Online publication date: 1-Aug-2011
https://dl.acm.org/doi/10.1007/s10878-009-9284-z
Cho MLu KYuan KPan D(2009)BoxRouter 2.0ACM Transactions on Design Automation of Electronic Systems10.1145/1497561.149757514:2(1-21)Online publication date: 7-Apr-2009
https://dl.acm.org/doi/10.1145/1497561.1497575
Wu MLin RTsai S(2008)Chip placement in a reticle for multiple-project wafer fabricationACM Transactions on Design Automation of Electronic Systems10.1145/1297666.129768813:1(1-21)Online publication date: 6-Feb-2008
https://dl.acm.org/doi/10.1145/1297666.1297688

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Bus-pin-aware bus-driven floorplanning

Redundant-wires-aware ECO timing and mask cost optimization

Thermal-aware bus-driven floorplanning

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Bus-pin-aware bus-driven floorplanning

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