Article

On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives

Authors:

K. Paulsson,

M. Hübner,

J. BeckerAuthors Info & Claims

SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design

Pages 173 - 178

https://doi.org/10.1145/1150343.1150389

Published: 28 August 2006 Publication History

Get Access

Abstract

The flexibility of reconfigurable hardware can be exploited to adapt to requirements of applications while run-time. Hardware described functions can be configured dynamically when required, which leads to better usage of chip resources due to reduction of chip area and therefore reduced power consumption. Unfortunately the many restrictions of available run-time reconfigurable hardware architectures has until now limited the integration of such systems in real applications. Also, the high power consumption of reconfigurable architectures makes them suitable for mostly very high performance requiring applications such as signal processing tasks or multimedia applications. In this paper a method for 2D reconfiguration is described, which also enables on-line routing of communication primitives. In order to decrease the power consumption, we also propose a method for adapting signal routing according to power and performance. We demonstrate that there is a trade-off between the power and performance of on-chip signal lines, which can be exploited for on-line adaptation.

References

[1]

L. Shang, S. A. S. Kaviani, K. Bathala "Dynamic Power Consumption in Virtex II FPGA Family," Proc. of the 2002 ACM/SIGDA 10th Int. Symp. on Field-Programmable Gate Arrays, pp. 157--164, 2002.

Digital Library

Google Scholar

[2]

J. Becker, M. Huebner, M. Ullmann, "Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-Time Systems," Proc. of the IFIP Int. Conf. on Very Large Scale Integration (VLSI-SoC), pp. 129--134, Dec. 2003

Google Scholar

[3]

M. Ullmann, M. Hübner, B. Grimm, J. Becker,"An FPGA Run-Time System for Dynamical On-Demand Reconfiguration," Proc. of the 11th Reconfigurable Architectures Workshop (RAW/IPDPS), April 2004.

Google Scholar

[4]

Xilinx Web Site. On-line at www.xilinx.com http://www.xilinx.com.

Google Scholar

[5]

M. Huebner, T. Becker, J. Becker: "Real-time LUT-based Network Topologies for dynamic and partial FPGA Self-Reconfiguration", SBCCI04, Porto de Galinhas, Brasil.

Digital Library

Google Scholar

[6]

M.Hübner, C. Schuck, M. Kühnle, J. Becker: "New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-Time Adaptive Microelectronic Circuits", ISVLSI2006, Karlsruhe, Germany.

Google Scholar

[7]

K. W. W. Poon, "Power Estimation for Field Programmable Gate Arrays," Master of Applied Science Dissertation, University of British Colombia, 2002.

Google Scholar

[8]

B. Blodget, S. McMillan: "A lightweight approach for embedded reconfiguration of FPGAs", DATE'03, Munich Germany.

Digital Library

Google Scholar

[9]

J. Becker, M. Hübner, K. Paulsson, A. Thomas: "Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics", ReCoSoC 2005, Montpellier, France.

Google Scholar

Cited By

View all

Liu SPittman RForin AGaudiot J(2013)Achieving energy efficiency through runtime partial reconfiguration on reconfigurable systemsACM Transactions on Embedded Computing Systems10.1145/2442116.244212212:3(1-21)Online publication date: 8-Apr-2013
https://dl.acm.org/doi/10.1145/2442116.2442122
Anwer JMeisner SPlatzner M(2013)Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)10.1109/ReConFig.2013.6732280(1-6)Online publication date: Dec-2013
https://doi.org/10.1109/ReConFig.2013.6732280
Cardoso JF. Coutinho JDiniz P(2013)Related WorkCompilation and Synthesis for Embedded Reconfigurable Systems10.1007/978-1-4614-4894-5_7(181-195)Online publication date: 17-May-2013
https://doi.org/10.1007/978-1-4614-4894-5_7
Show More Cited By

Index Terms

On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives
1. Hardware
  1. Communication hardware, interfaces and storage

Recommendations

Supply and power optimization in leakage-dominant technologies

In this paper, we present a methodology for systematically optimizing the power-supply voltage for either maximizing the performance of very large scale integration (VLSI) circuits or minimizing the power dissipation in technologies where leakage power ...
Clock Power Analysis of Low Power Clock Gated Arithmetic Logic Unit on Different FPGA
CICN '14: Proceedings of the 2014 International Conference on Computational Intelligence and Communication Networks

This paper, deals with Latch Free Clock Gating technique for reduction of clock power and total power consumption in Low Power Arithmetic and Logic Unit and we have analysed power reduction on different FPGA devices. Without latch free clock gating ...
Performance Evaluation of FIR Filter After Implementation on Different FPGA and SOC and Its Utilization in Communication and Network

There are many areas of communication and network, which have open scope to use FIR filter. Therefore, energy efficient FIR filter will increase lifetime of network and FIR filter with less delay and latency will increase performance of network. In this ...

Comments

Information & Contributors

Information

Published In

SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design

August 2006

248 pages

ISBN:1595934790

DOI:10.1145/1150343

General Chair:
Claudionor Coelho
Universidade de Minas Gerais, Brazil
,
Program Chairs:
Ricardo Jacobi
Universidade de Brasilia, Brazil
,
Juergen Becker
Universitaet Karlsruhe (TH), Germany

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 28 August 2006

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

SBCCI06

Sponsor:

SBCCI06: 19th Symposium on Integrated Circuits and System Design

August 28 - September 1, 2006

MG, Ouro Preto, Brazil

Acceptance Rates

Overall Acceptance Rate 133 of 347 submissions, 38%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

20
Total Citations
View Citations
366
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)0

Reflects downloads up to 26 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Liu SPittman RForin AGaudiot J(2013)Achieving energy efficiency through runtime partial reconfiguration on reconfigurable systemsACM Transactions on Embedded Computing Systems10.1145/2442116.244212212:3(1-21)Online publication date: 8-Apr-2013
https://dl.acm.org/doi/10.1145/2442116.2442122
Anwer JMeisner SPlatzner M(2013)Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)10.1109/ReConFig.2013.6732280(1-6)Online publication date: Dec-2013
https://doi.org/10.1109/ReConFig.2013.6732280
Cardoso JF. Coutinho JDiniz P(2013)Related WorkCompilation and Synthesis for Embedded Reconfigurable Systems10.1007/978-1-4614-4894-5_7(181-195)Online publication date: 17-May-2013
https://doi.org/10.1007/978-1-4614-4894-5_7
Osborne WLuk WCoutinho JMencer O(2011)Energy reduction by systematic run-time reconfigurable hardware deactivationTransactions on High-Performance Embedded Architectures and Compilers IV10.5555/2172445.2172467(354-369)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.5555/2172445.2172467
Jevtic RCarreras C(2011)Power Measurement Methodology for FPGA DevicesIEEE Transactions on Instrumentation and Measurement10.1109/TIM.2010.204766460:1(237-247)Online publication date: Jan-2011
https://doi.org/10.1109/TIM.2010.2047664
Sironi FCuoccio A(2011)Self-aware adaptation via implementation hot-swap for heterogeneous computingProceedings of the 2011 1st International Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-Oriented Environments10.1109/CHANGE.2011.6172449(1-8)Online publication date: 6-Mar-2011
https://dl.acm.org/doi/10.1109/CHANGE.2011.6172449
Jara-Berrocal AGordon-Ross A(2011)An integrated development toolset and implementation methodology for partially reconfigurable system-on-chipsProceedings of the ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors10.1109/ASAP.2011.6043272(219-222)Online publication date: 11-Sep-2011
https://dl.acm.org/doi/10.1109/ASAP.2011.6043272
Osborne WLuk WCoutinho JMencer O(2011)Energy Reduction by Systematic Run-Time Reconfigurable Hardware DeactivationTransactions on High-Performance Embedded Architectures and Compilers IV10.1007/978-3-642-24568-8_18(354-369)Online publication date: 2011
https://doi.org/10.1007/978-3-642-24568-8_18
Sironi FTriverio MHoffmann HMaggio MSantambrogio M(2010)Self-Aware Adaptation in FPGA-based SystemsProceedings of the 2010 International Conference on Field Programmable Logic and Applications10.1109/FPL.2010.43(187-192)Online publication date: 31-Aug-2010
https://dl.acm.org/doi/10.1109/FPL.2010.43
Paulsson KHübner MBecker J(2009)Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systemsMicroprocessors & Microsystems10.1016/j.micpro.2008.08.00633:1(46-52)Online publication date: 1-Feb-2009
https://dl.acm.org/doi/10.1016/j.micpro.2008.08.006
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Supply and power optimization in leakage-dominant technologies

Clock Power Analysis of Low Power Clock Gated Arithmetic Logic Unit on Different FPGA

Performance Evaluation of FIR Filter After Implementation on Different FPGA and SOC and Its Utilization in Communication and Network

Comments

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Other Metrics

Article Metrics

Other Metrics

Cited By

Login options

Full Access

PDF

eReader

Abstract

References

Cited By

Index Terms

Recommendations

Supply and power optimization in leakage-dominant technologies

Clock Power Analysis of Low Power Clock Gated Arithmetic Logic Unit on Different FPGA

Performance Evaluation of FIR Filter After Implementation on Different FPGA and SOC and Its Utilization in Communication and Network

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations