Article

Automatic selection of application-specific instruction-set extensions

Authors:

Elena Moscu Panainte,

Stamatis VassiliadisAuthors Info & Claims

CODES+ISSS '06: Proceedings of the 4th international conference on Hardware/software codesign and system synthesis

Pages 160 - 165

https://doi.org/10.1145/1176254.1176293

Published: 22 October 2006 Publication History

Abstract

In this paper, we present a general and an efficient algorithm for automatic selection of new application-specific instructions under hardware resources constraints. The instruction selection is formulated as an ILP problem and efficient solvers can be used for finding the optimal solution. An important feature of our algorithm is that it is not restricted to basic-block level nor does it impose any limitation on the number of the newly added instructions or on the number of the inputs/outputs of these instructions. The presented results show that a significant overall application speedup is achieved even for large kernels (for ADPCM decoder the speedup ranges from x1.2 to x3.7) and that our algorithm compares well with other state-of-art algorithms for automatic instruction set extensions.

References

[1]

C. Alippi, W. Fornaciari, L. Pozzi, and M. Sami. A DAG-Based Design Approach for Reconfigurable VLIW Processors. In Proceedings of DATE 1999, pages 778--779, Munich, Germany, March 1999.

Digital Library

[2]

M. Arnold and H. Corporaal. Design Domain Specific Processors. In Proceedings of the 9th International Workshop on Hardware/Software CoDesign, pages 61--66, April 2001.

Digital Library

[3]

K. Atasu, G. Dündar, and C. ÖOzturan. An Integer Linear Programming Approach for Identifying Instruction-Set Extensions. In Proceedings of CODES+ISSS'05, pages 172--177, New Jersey, USA, September 2005.

Digital Library

[4]

K. Atasu, L. Pozzi, and P. Ienne. Automatic Application-Specific Instruction-Set Extensions under Microarchitectural Constraints. In Proceedings of 40th DAC, pages 256--261, Anaheim, California, June 2003.

Digital Library

[5]

M. Baleani, F. Gennari, Y. Jiang, Y. Pate, R. K. Brayton, and A. Sangiovanni-Vincentelli. HW/SW Partitioning and Code Generation of Embedded Control Application on a Reconfigurable Architecture Platform. In Proceedings of the 10th International Workshop on Hardware/Software Codesign, pages 151--156, Estes Park, Colo., May 2002.

Digital Library

[6]

P. Brisk, A. Kaplan, R. Kastner, and M. Sarrafzadeh. Instruction Generation and Regularity Extraction for Reconfigurable Processors. In Proceedings of CASES 2002, pages 262--269, Grenoble, France, 2002.

Digital Library

[7]

H. Choi, J. S. Kim, C. W. Yoon, I. C. Park, S. H. Hwang, and C. M. Kyung. Synthesis of Application Specific Instructions for Embedded DSP Software. IEEE Transactions on Computers, 48(6):603--614, June 1999.

Digital Library

[8]

N. Clark, H. Zhong, and S. Mahlke. Processor Acceleration Through Automated Instruction Set Customization. In Proceedings of the 36th MICRO, pages 129--140, December 2003.

Digital Library

[9]

J. Cong, Y. Fan, G. Han, and Z. Zhang. Application Specific Instruction Generation for Configurable Processor Architectures. In Proceedings of FPGA'04, pages 183--189, Monterey, California, February 2004.

Digital Library

[10]

D. Goodwin and D. Petkov. Automatic Generation of Application Specific Processors. In Proceedings of CASES'03, pages 137--147, San Jose, California, 30 Oct. - 1 Nov. 2003.

Digital Library

[11]

R. Kastner, A. Kaplan, S. O. Memik, and E. Bozorgzadeh. Instruction Generation for Hybrid Reconfigurable System. ACM Transactions on Design Automation of Embedded Systems, 7(4):605--627, October 2002.

Digital Library

[12]

C. Lee, M. Potkonjak, and W. H. Mangione-Smith. MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communicatons Systems. In International Symposium on Microarchitecture, pages 330--335, 1997.

Digital Library

[13]

F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha. Synthesis of Custom Processors Based on Extensible Platforms. Proceedings of ICCAD 2002, pages 641--648, November 2002.

Digital Library

[14]

S. Vassiliadis, S. Wong, G. N. Gaydadjiev, K. Bertels, G. Kuzmanov, and E. M. Panainte. The Molen Polymorphic Processor. IEEE Transactions on Computers, 53(11):1363-- 1375, November 2004.

Digital Library

[15]

P. Yu and T. Mitra. Scalable Custom Instructions Identification for Instruction-Set Extensible Processors. In Proceedings of CASES'04, pages 69--78, 2004.

Digital Library

Cited By

Wang SXiao C(2024)Reinforcement Learning for Selecting Custom Instructions Under Area ConstraintIEEE Transactions on Artificial Intelligence10.1109/TAI.2023.33080995:4(1882-1894)Online publication date: Apr-2024
https://doi.org/10.1109/TAI.2023.3308099
Hussein EWaschneck BMayr C(2024)Automating application-driven customization of ASIPs: A surveyJournal of Systems Architecture10.1016/j.sysarc.2024.103080148(103080)Online publication date: Mar-2024
https://doi.org/10.1016/j.sysarc.2024.103080
Pilato CSoldavini S(2022)Accelerator Design with High-Level SynthesisHandbook of Computer Architecture10.1007/978-981-15-6401-7_19-1(1-33)Online publication date: 27-Jan-2022
https://doi.org/10.1007/978-981-15-6401-7_19-1
Show More Cited By

Recommendations

The Instruction-Set Extension Problem: A Survey

The extension of a given instruction-set with specialized instructions has become a common technique used to speed up the execution of applications. By identifying computationally intensive portions of an application to be partitioned in segments of ...
Automatic custom instruction identification for application-specific instruction set processors

The application-specific instruction set processors (ASIPs) have received more and more attention in recent years. ASIPs make trade-offs between flexibility and performance by extending the base instruction set of a general-purpose processor with custom ...
Selection of instruction set extensions for an FPGA embedded processor core
IPDPS'06: Proceedings of the 20th international conference on Parallel and distributed processing

A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The instruction set of the PowerPC 405 is extended by selecting additional ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

CODES+ISSS '06: Proceedings of the 4th international conference on Hardware/software codesign and system synthesis

October 2006

328 pages

ISBN:1595933700

DOI:10.1145/1176254

General Chair:
Reinaldo Bergamaschi
IBM T. J. Watson Research Center, USA
,
Program Chair:
Kiyoung Choi
Seoul National University, Korea

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 October 2006

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

ESWEEK06

Sponsor:

ESWEEK06: Second Embedded Systems Week 2006

October 22 - 25, 2006

Seoul, Korea

Acceptance Rates

Overall Acceptance Rate 280 of 864 submissions, 32%

Upcoming Conference

ESWEEK '24

Sponsor:
sigbed
sigbed
sigbed

Twentieth Embedded Systems Week

September 29 - October 4, 2024

Raleigh , NC , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

35
Total Citations
View Citations
379
Total Downloads

Downloads (Last 12 months)5
Downloads (Last 6 weeks)0

Reflects downloads up to 12 Aug 2024

Other Metrics

View Author Metrics

Citations

Cited By

Wang SXiao C(2024)Reinforcement Learning for Selecting Custom Instructions Under Area ConstraintIEEE Transactions on Artificial Intelligence10.1109/TAI.2023.33080995:4(1882-1894)Online publication date: Apr-2024
https://doi.org/10.1109/TAI.2023.3308099
Hussein EWaschneck BMayr C(2024)Automating application-driven customization of ASIPs: A surveyJournal of Systems Architecture10.1016/j.sysarc.2024.103080148(103080)Online publication date: Mar-2024
https://doi.org/10.1016/j.sysarc.2024.103080
Pilato CSoldavini S(2022)Accelerator Design with High-Level SynthesisHandbook of Computer Architecture10.1007/978-981-15-6401-7_19-1(1-33)Online publication date: 27-Jan-2022
https://doi.org/10.1007/978-981-15-6401-7_19-1
Zacharopoulos GFerretti LGiaquinta EAnsaloni GPozzi L(2019)RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source CodeIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.281868938:4(741-754)Online publication date: Apr-2019
https://doi.org/10.1109/TCAD.2018.2818689
Qin YWang HJia ZXia H(2016)A flexible and scalable implementation of elliptic curve cryptography over GF(p) based on ASIP2016 IEEE 35th International Performance Computing and Communications Conference (IPCCC)10.1109/PCCC.2016.7820654(1-8)Online publication date: Dec-2016
https://doi.org/10.1109/PCCC.2016.7820654
Wang SXiao CLiu WCasseau EYang X(2015)Selecting most profitable instruction-set extensions using ant colony heuristic2015 Conference on Design and Architectures for Signal and Image Processing (DASIP)10.1109/DASIP.2015.7367250(1-7)Online publication date: Sep-2015
https://doi.org/10.1109/DASIP.2015.7367250
Lam SSrikanthan TClarke C(2014)Rapid evaluation of custom instruction selection approaches with FPGA estimationACM Transactions on Embedded Computing Systems10.1145/256001413:4(1-29)Online publication date: 10-Mar-2014
https://dl.acm.org/doi/10.1145/2560014
Nowatzki TFerris MSankaralingam KEstan CVaish NWood D(2013)Optimization and Mathematical Modeling in Computer ArchitectureSynthesis Lectures on Computer Architecture10.2200/S00531ED1V01Y201308CAC0268:4(1-144)Online publication date: 30-Sep-2013
https://doi.org/10.2200/S00531ED1V01Y201308CAC026
Ragel RRadhakrishnan SAmbrose JParameswaran S(2013)A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set ProcessorsProceedings of the 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems10.1109/VLSID.2013.154(7-12)Online publication date: 5-Jan-2013
https://dl.acm.org/doi/10.1109/VLSID.2013.154
Martin KWolinski CKuchcinski KFloch ACharot F(2012)Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application CompilationACM Transactions on Reconfigurable Technology and Systems10.1145/2209285.22092895:2(1-38)Online publication date: 1-Jun-2012
https://dl.acm.org/doi/10.1145/2209285.2209289
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents