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Profile-driven energy reduction in network-on-chips

Published: 10 June 2007 Publication History

Abstract

Reducing energy consumption of a Network-on-Chip (NoC) is a critical design goal, especially for power-constrained embedded systems.In response, prior research has proposed several circuit/architectural level mechanisms to reduce NoC power consumption. This paper considers the problem from a different perspective and demonstrates that compiler analysis can be very helpful for enhancing the effectiveness of a hardware-based link power management mechanism by increasing the duration of communication links' idle periods. The proposed profile-based approach achieves its goal by maximizing the communication link reuse through compiler-directed, static message re-routing. That is, it clusters the required data communications into a small set of communication links at any given time, which increases the idle periods for the remaining communication links in the network. This helps hardware shut down more communication links and their corresponding buffers to reduce leakage power. The current experimental evaluation, with twelve data-intensive embedded applications, shows that the proposed profile-driven compiler approach reduces leakage energy by more than 35% (on average) as compared to a pure hardware-based link power management scheme.

References

[1]
G. Ascia, V. Catania, and M. Palesi. Multi-objective mapping for mesh-based NoC architectures. In Proc. International Conference on Hardware/Software Codesign and System Synthesis, Sept. 2004.
[2]
L. Benini and G. D. Micheli. Powering networks on chips: energy-efficient and reliable interconnect design for SoCs. In Proc. the 14th Int. Symp. on Systems Synthesis, 2001.
[3]
G. Chen, F. Li, and M. Kandemir. Compiler-directed channel allocation for saving power in on-chip networks. In Proc. 33rd Annual Symposium on Principles of Programming Languages, 2006.
[4]
G. Chen, F. Li, M. Kandemir, and M. J. Irwin. Reducing noc energy consumption through compiler-directed channel voltage scaling. In Proc. the 2006 ACM SIGPLAN conference on Programming Language Design and Implementation, pages 193--203, New York, NY, USA, 2006. ACM Press.
[5]
X. Chen and L.-S. Peh. Leakage power modeling and optimization in interconnection networks. In Proc. the Int. Symp. on Low Power and Electronics Design, Aug. 2003.
[6]
W. J. Dally and C. L. Seitz. Deadlock-free message routing in multiprocessor interconnection networks. IEEE Trans. Comput., 36(5):547--553, 1987.
[7]
W. J. Dally and B. Towles. Route packets, not wires: on-chip interconnection networks. In Proc. the 38th Conf. on Design Automation, 2001.
[8]
J. Duato. A new theory of deadlock-free adaptive routing in wormhole networks. IEEE Trans. Parallel and Distributed Systems, 4(12):1320--1331, 1993.
[9]
J. B. Duato, S. Yalamanchili, and L. Ni. Interconnection Networks. Morgan Kaufmann Publishers, 2002.
[10]
N. Eisley and L.-S. Peh. High-level power analysis of on-chip networks. In Proc. the 7th Int. Conf. on Compilers, Architectures and Synthesis for Embedded Systems, Sept. 2004.
[11]
PSM. et al. Simics: A full system simulation platform. Computer, 35(2):50--58, 2002.
[12]
A. Hansson, K. Goossens, and A. Rpdulescu. A unified approach to constrained mapping and routing on network-on-chip architectures. In Proc. International Conference on Hardware/Software Co-Design and System Synthesis, 2005.
[13]
J. Hu and R. Marculescu. Energy- and performance-aware mapping for regular NoC architectures. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 24(4), Apr. 2005.
[14]
A. Jalabert, S. Murali, L. Benini, and G.D. Michieli. XpipesCompiler: A tool for instantiating application specific Networks-on-Chip. In Proc. the Conf. on Design, Automation and Test in Europe, 2004.
[15]
E.J. Kim, K.H. Yum, G. Link, N. Vijaykrishnan, M. Kandemir, M.J. Irwin, M. Yousif, and CR. Das. Energy optimization techniques in cluster interconnects. In Proc. the Int. Symp. on Low Power Electronics and Design, Aug. 2003.
[16]
http://cares.icsl.ucla.edu/MediaBench/.
[17]
http://www.eecs.umich.edu/mibench/.
[18]
S.S. Mukherjee, P. Bannon, S. Lang, A. Spink, and D. Webb. The alpha 21364 network architecture. IEEE Micro, 22(1), Jan. 2002.
[19]
R. Nagarajan, D. Burger, K.S. McKinley, C. Lin, S.W. Keckler, and S.K. Kushwaha. Static placement, dynamic issue (SPDI) scheduling for EDGE architectures. In Proc. International Conference on Parallel Architectures and Compilation Techniques, Oct. 2004.
[20]
U. Ogras, J. Hu, and R. Marculescu. Key research problem in NoC design: A holistic perspective. In Proc. International Conference on Hardware/Software Co-Design and System Synthesis, 2005.
[21]
C.S. Patel. Power constrained design of multiprocessor interconnection networks. In Proc. the Int. Conf. on Computer Design, Washington, DC, USA, 1997.
[22]
V. Raghunathan, M.B. Srivastava, and R.K. Gupta. A survey of techniques for energy efficient on-chip communication. In Proc. the 40th Design Automation Conference, 2003.
[23]
L. Shang, L.-S. Peh, and N.K. Jha. Dynamic voltage scaling with links for power optimization of interconnection networks. In Proc. International Symposium on High-Performance Computer Architecture, Feb. 2003.
[24]
D. Shin and J. Kim. Power-aware communication optimization for networks-on-chips with voltage scalable links. In Proc. Intl. Conf. on Hardware/Software Codesign and System Synthesis, 2004.
[25]
T. Simunic and S. Boyd. Managing power consumption in networks on chip. In Proc. the Conf. on Design, Automation and Test in Europe, 2002.
[26]
V. Soteriou and L.-S. Peh. Dynamic power management for power optimization of interconnection networks using on/off links. In Proc. Symposium on High Performance Interconnects, 2003.
[27]
V. Soteriou and L.-S. Peh. Design space exploration of power-aware on/off interconnection networks. In Proc. the 22nd Int. Conf. on Computer Design, Oct. 2004.
[28]
M.B. Taylor and et al. The RAW microprocessor: A computational fabric for software circuits and general purpose programs. IEEE Micro, 22(2), 2002.
[29]
http://www-unix.mcs.anl.gov/mpi/.
[30]
http://www.ece.northwestern.edu/cpdc/Paradigm/Paradigm.html.
[31]
H.-S. Wang, X. Zhu, L.-S. Peh, and S. Malik. Orion: A power-performance simulator for interconnection networks. In Proc. the 35th Int. Symp. on Microarchitecture, Nov. 2002.
[32]
F. Worm, P. Ienne, P. Thiran, and G.D. Micheli. An adaptive low power transmission scheme for on-chip networks. In Proc. International System Synthesis Symposium, 2002.
[33]
N.D. Zervas, K. Masselos, and C. Goutis. Code transformations for embedded multimedia applications: impact on power and performance. In Proc. ISCA Power-Driven Microarchitecture Workshop, 1998.

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  • (2021)Compiler support for near data computingProceedings of the 26th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/3437801.3441600(90-104)Online publication date: 17-Feb-2021
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  • (2015)Design Intelligence for Interconnection Realization in Power-Managed SoCsComputational Intelligence in Digital and Network Designs and Applications10.1007/978-3-319-20071-2_3(69-96)Online publication date: 15-Jul-2015
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    Published In

    cover image ACM SIGPLAN Notices
    ACM SIGPLAN Notices  Volume 42, Issue 6
    Proceedings of the 2007 PLDI conference
    June 2007
    491 pages
    ISSN:0362-1340
    EISSN:1558-1160
    DOI:10.1145/1273442
    Issue’s Table of Contents
    • cover image ACM Conferences
      PLDI '07: Proceedings of the 28th ACM SIGPLAN Conference on Programming Language Design and Implementation
      June 2007
      508 pages
      ISBN:9781595936332
      DOI:10.1145/1250734
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 10 June 2007
    Published in SIGPLAN Volume 42, Issue 6

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    Author Tags

    1. Network-on-Chip
    2. compiler
    3. power
    4. routing

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    • (2021)Compiler support for near data computingProceedings of the 26th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/3437801.3441600(90-104)Online publication date: 17-Feb-2021
    • (2021)UPR: deadlock-free dynamic network reconfiguration by exploiting channel dependency graph compatibilityThe Journal of Supercomputing10.1007/s11227-021-03791-8Online publication date: 14-Apr-2021
    • (2015)Design Intelligence for Interconnection Realization in Power-Managed SoCsComputational Intelligence in Digital and Network Designs and Applications10.1007/978-3-319-20071-2_3(69-96)Online publication date: 15-Jul-2015
    • (2013)Enabling power efficiency through dynamic rerouting on-chipACM Transactions on Embedded Computing Systems10.1145/2485984.248599912:4(1-23)Online publication date: 3-Jul-2013
    • (2021)UPR: deadlock-free dynamic network reconfiguration by exploiting channel dependency graph compatibilityThe Journal of Supercomputing10.1007/s11227-021-03791-8Online publication date: 14-Apr-2021
    • (2018)Quantifying and Optimizing Data Access Parallelism on Manycores2018 IEEE 26th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS)10.1109/MASCOTS.2018.00022(131-144)Online publication date: Sep-2018
    • (2011)Communication based proactive link power managementTransactions on High-Performance Embedded Architectures and Compilers IV10.5555/2172445.2172454(135-154)Online publication date: 1-Jan-2011
    • (2011)Communication Based Proactive Link Power ManagementTransactions on High-Performance Embedded Architectures and Compilers IV10.1007/978-3-642-24568-8_7(135-154)Online publication date: 2011
    • (2010)Compiler directed network-on-chip reliability enhancement for chip multiprocessorsACM SIGPLAN Notices10.1145/1755951.175590245:4(85-94)Online publication date: 13-Apr-2010
    • (2010)Compiler directed network-on-chip reliability enhancement for chip multiprocessorsProceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems10.1145/1755888.1755902(85-94)Online publication date: 13-Apr-2010
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