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View all- Hwang MJung SRoy K(2009)Slope interconnect effortIEEE Transactions on Circuits and Systems Part I: Regular Papers10.1109/TCSI.2008.200621756:7(1427-1440)Online publication date: 1-Jul-2009
Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates
Pages 387 - 390
Abstract
We present a circuit delay framework in a closed form that accounts for the dynamic behavior of signal slope in subthreshold (VDD < VT) as well as superthreshold (VDD > VT) regions. The proposed model converts a signal slope into its effective fanout for delay estimation. Simulations show that for ISCAS benchmark circuits, our framework exhibits a speedup of three orders of magnitude over HSPICE with 5% error. Measured results in 65nm show that for a wide range of interconnect lengths and geometries, the proposed model predicts the circuit delay with 5.7% error at the supply voltage of VDD = 1.2V, and with 4.5% error at VDD = 0.4V .
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Index Terms
- Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates
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Published In
August 2007
432 pages
ISBN:9781595937094
DOI:10.1145/1283780
- General Chairs:
- Diana Marculescu,
- Anand Raghunathan,
- Program Chairs:
- Ali Keshavarzi,
- Vijaykrishnan Narayanan
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Publication History
Published: 27 August 2007
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ISLPED07: International Symposium on Low Power Electronics and Design
August 27 - 29, 2007
OR, Portland, USA
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Overall Acceptance Rate 398 of 1,159 submissions, 34%
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View all- Hwang MJung SRoy K(2009)Slope interconnect effortIEEE Transactions on Circuits and Systems Part I: Regular Papers10.1109/TCSI.2008.200621756:7(1427-1440)Online publication date: 1-Jul-2009
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