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Timing-driven N-way decomposition

Published: 10 May 2009 Publication History

Abstract

Logic decomposition has been extensively used to optimize the worst-case delay and the area in the technology independent phase. Bi-decomposition is one of the state-of-art techniques to reduce the depth of the netlist due to the affordable computational cost. We present a novel n-way decomposition technique that improves bi-decomposition. The problem of decomposition is formulated as a Boolean relation which captures a larger set of possible solutions compared to bi-decomposition. The solution obtained from the Boolean relation improves the delay with near-zero cost in area. As it is shown on the experimental results, a considerable improvement is achieved on large netlists and even larger depending on which technology mapper is used.

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cover image ACM Conferences
GLSVLSI '09: Proceedings of the 19th ACM Great Lakes symposium on VLSI
May 2009
558 pages
ISBN:9781605585222
DOI:10.1145/1531542
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Publication History

Published: 10 May 2009

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Author Tags

  1. decomposition
  2. logic design
  3. timing optimization

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GLSVLSI '09
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GLSVLSI '09: Great Lakes Symposium on VLSI 2009
May 10 - 12, 2009
MA, Boston Area, USA

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