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Slotless module-based reconfiguration of embedded FPGAs

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J. RiceAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 9, Issue 1

Article No.: 6, Pages 1 - 26

https://doi.org/10.1145/1596532.1596538

Published: 29 October 2009 Publication History

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Abstract

The difficult aspect of hardware reconfiguration is not creating the computational blocks, which are generally available from FPGA vendors and third parties, but linking the blocks in a manner that suits each application's unique connectivity, bandwidth, and latency requirements. Our approach uses the standard Xilinx implementation tools to generate dynamic module partial bitstreams, but choosing the module's coordinates and completing connections to other modules are runtime operations. Scripts automatically add interface wrappers to dynamic modules and generate a library of relocatable partial bitstreams. The library is used by an efficient runtime system that completes application requests for instancing and connecting modules, effectively insulating the designer from FPGA reconfiguration complexities. In this way, a large sandbox may be allocated to dynamic modules rather than fixed module slots and interconnect. Application engineers interact with the Wires on Demand (WoD) system through a runtime software API, and do not have to master hardware description languages and implementation tools.

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Cited By

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Zhang HBauer LKochte MSchneider EWunderlich HHenkel J(2017)Aging Resilience and Fault Tolerance in Runtime Reconfigurable ArchitecturesIEEE Transactions on Computers10.1109/TC.2016.261640566:6(957-970)Online publication date: 1-Jun-2017
https://dl.acm.org/doi/10.1109/TC.2016.2616405
Gong LDiessel OGong LDiessel O(2014)Verification ChallengesFunctional Verification of Dynamically Reconfigurable FPGA-based Systems10.1007/978-3-319-06838-1_2(15-40)Online publication date: 22-Jul-2014
https://doi.org/10.1007/978-3-319-06838-1_2
Chandrasekharan ARajagopalan SSubbarayan GFrangieh TIskander YCraven SPatterson C(2010)Accelerating FPGA development through the automatic parallel application of standard implementation tools2010 International Conference on Field-Programmable Technology10.1109/FPT.2010.5681754(53-60)Online publication date: Dec-2010
https://doi.org/10.1109/FPT.2010.5681754

Index Terms

Slotless module-based reconfiguration of embedded FPGAs
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Signal processing systems
  2. Electronic design automation
    1. High-level and register-transfer level synthesis

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Reviews

Reviewer: Junqing Sun

Field-programmable gate array (FPGA)-based reconfigurable computing has proven to be successful in the areas of biochemistry, linear algebra, and digital signal processing (DSP). Both high-performance computation units and efficient interconnections are important to the FPGA accelerator's final performance. In the past few years, numerous high-performance intellectual property (IP) cores have been developed, for different applications. This paper proposes a runtime system that automatically configures suitable connections for IP cores, and ultimately helps to develop a friendly programming model that can automatically build up the system using existing IPs. Compared to general-purpose central processing units (CPUs) and other types of accelerators, such as graphics processing units (GPUs) and cell processors, FPGAs require the most development effort, although they provide the finest-tuned architectures. FPGA developers need to have a solid knowledge of hardware; the lack of programming models isolates programmers from hardware details, thus preventing FPGA accelerators' popularity. Therefore, automatically connecting existing IPs will allow FPGA accelerators to be more widely applied. The authors briefly cover several different aspects of their project. Readers who are unfamiliar with this project may find it difficult to follow the paper. Overall, since the paper presents new ideas on FPGA synthesis for reconfigurable computing, it should interest readers who work in the field. Online Computing Reviews Service

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cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 9, Issue 1

October 2009

184 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/1596532

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 29 October 2009

Accepted: 01 January 2009

Revised: 01 December 2008

Received: 01 June 2008

Published in TECS Volume 9, Issue 1

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Zhang HBauer LKochte MSchneider EWunderlich HHenkel J(2017)Aging Resilience and Fault Tolerance in Runtime Reconfigurable ArchitecturesIEEE Transactions on Computers10.1109/TC.2016.261640566:6(957-970)Online publication date: 1-Jun-2017
https://dl.acm.org/doi/10.1109/TC.2016.2616405
Gong LDiessel OGong LDiessel O(2014)Verification ChallengesFunctional Verification of Dynamically Reconfigurable FPGA-based Systems10.1007/978-3-319-06838-1_2(15-40)Online publication date: 22-Jul-2014
https://doi.org/10.1007/978-3-319-06838-1_2
Chandrasekharan ARajagopalan SSubbarayan GFrangieh TIskander YCraven SPatterson C(2010)Accelerating FPGA development through the automatic parallel application of standard implementation tools2010 International Conference on Field-Programmable Technology10.1109/FPT.2010.5681754(53-60)Online publication date: Dec-2010
https://doi.org/10.1109/FPT.2010.5681754

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Dynamic Reconfiguration Technologies Based on FPGA in Software Defined Radio System

A Lightweight Approach for Embedded Reconfiguration of FPGAs

Self-Reconfigurable Embedded Systems on Low-Cost FPGAs

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Dynamic Reconfiguration Technologies Based on FPGA in Software Defined Radio System

A Lightweight Approach for Embedded Reconfiguration of FPGAs

Self-Reconfigurable Embedded Systems on Low-Cost FPGAs

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