research-article

Evaluating design trade-offs in customizable processors

Authors:

Unmesh D. Bordoloi,

Huynh Phung Huynh,

Samarjit Chakraborty,

Tulika MitraAuthors Info & Claims

DAC '09: Proceedings of the 46th Annual Design Automation Conference

Pages 244 - 249

https://doi.org/10.1145/1629911.1629978

Published: 26 July 2009 Publication History

Abstract

The short time-to-market window for embedded systems demands automation of design methodologies for customizable processors. Recent research advances in this direction have mostly focused on single criteria optimization, e.g., optimizing performance though custom instructions under pre-defined area constraint. From the designer's perspective, however, it would be more interesting if the conflicting trade-offs among multiple objectives (e.g., performance versus area) are exposed enabling an informed decision making. Unfortunately, identifying the optimal trade-off points turns out to be computationally intractable. In this paper, we present a polynomial-time approximation algorithm to systematically evaluate the design trade-offs. In particular, we explore performance-area trade-offs in the context of multitasking real-time embedded applications to be implemented on a customizable processor.

References

[1]

M. Arnold and H. Corporaal. Designing domain-specific processors. In CODES, 2001.

Digital Library

[2]

K. Atasu, L. Pozzi, and P. Ienne. Automatic application-specific instruction-set extensions under microarchitectural constraints. In DAC, 2003.

Digital Library

[3]

S. Baruah, A. K. Mok, and L. E. Rosier. Preemptively scheduling hard-real-time sporadic tasks on one processor. In RTSS, 1990.

[4]

N. Cheung, S. Parameswaran, and J. Henkel. INSIDE: INstruction Selection/Identification&Design Exploration for extensible processors. In ICCAD, 2002.

Digital Library

[5]

N. Clark, H. Zhong, and S. Mahlke. Processor acceleration through automated instruction set customization. In MICRO, 2003.

Digital Library

[6]

J. Cong, Y. Fan, G. Han, and Z. Zhang. Application-specific instruction generation for configurable processor architectures. In FPGA, 2004.

Digital Library

[7]

K. Deb. Multi-Objective Optimization Using Evolutionary Algorithms. John Wiley&Sons, 2001.

Digital Library

[8]

M. R. Guthaus et al. Mibench: A free, commercially representative embedded benchmark suite. In IEEE Annual Workshop on Workload Characterization, 2001.

Digital Library

[9]

H. P. Huynh and T. Mitra. Instruction-set customization for real-time systems. In DATE, 2007.

Digital Library

[10]

C. Lee, M. Potkonjak, and W. H. Mangione-Smith. Mediabench: a tool for evaluating and synthesizing multimedia and communicatons systems. In MICRO, 1997.

Digital Library

[11]

J. Lee, K. Choi, and N. Dutt. Efficient instruction encoding for automatic instruction set design of configurable ASIPs. In ICCAD, 2002.

Digital Library

[12]

C. L. Liu and James W. Layland. Scheduling algorithms for multiprogramming in a hard-real-time environment. Journal of the ACM, 20(1):46--61, 1973.

Digital Library

[13]

C. H. Papadimitriou and M. Yannakakis. On the approximability of trade-offs and optimal access of web sources. In FOCS, 2000.

Digital Library

[14]

F. Stappert. WCET benchmarks. http://www.c-lab.de/home/en/download.html.

[15]

Tensilica - XPRES Compiler - Optimized Hardware Directly from C. www.tensilica.com/products/devtools/hw_dev/xpres/.

[16]

Trimaran: An infrastructure for research in backend compilation and architecture exploration. http://www.trimaran.org.

[17]

P. Yu and T. Mitra. Scalable custom instructions identification for instruction-set extensible processors. In CASES, 2004.

Digital Library

[18]

P. Yu and T. Mitra. Satisfying real-time constraints with custom instructions. In CODES+ISSS, 2005.

Digital Library

Cited By

Mitra T(2017)Application-Specific ProcessorsHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_13-1(1-33)Online publication date: 8-Apr-2017
https://doi.org/10.1007/978-94-017-7358-4_13-1
Mitra T(2017)Application-Specific ProcessorsHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_13(377-409)Online publication date: 27-Sep-2017
https://doi.org/10.1007/978-94-017-7267-9_13
Zhong GVenkataramani VLiang YMitra TNiar S(2014)Design space exploration of multiple loops on FPGAs using high level synthesis2014 IEEE 32nd International Conference on Computer Design (ICCD)10.1109/ICCD.2014.6974719(456-463)Online publication date: Oct-2014
https://doi.org/10.1109/ICCD.2014.6974719
Show More Cited By

Index Terms

Evaluating design trade-offs in customizable processors
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems

Recommendations

Utilizing custom registers in application-specific instruction set processors for register spills elimination
GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI

Application-specific instruction set processor (ASIP) has become an important design choice for embedded systems. It can achieve both high flexibility offered by the base processor core and high performance and energy efficiency offered by the dedicated ...
Interactive exploration of design trade-offs

Typical design for manufacturing applications requires simultaneous optimization of conflicting performance objectives: Design variations that improve one performance metric may decrease another performance metric. In these scenarios, there is no unique ...
Efficient ASIP design for configurable processors with fine-grained resource sharing
FPGA '08: Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays

Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custom instructions. Several ASIP design automation flows have been proposed recently. In this paper, we investigate two techniques to improve these flows, so ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '09: Proceedings of the 46th Annual Design Automation Conference

July 2009

994 pages

ISBN:9781605584973

DOI:10.1145/1629911

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 26 July 2009

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

DAC '09

Sponsor:

EDAC
SIGDA
IEEE-CAS

DAC '09: The 46th Annual Design Automation Conference 2009

July 26 - 31, 2009

California, San Francisco

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

11
Total Citations
View Citations
140
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)1

Reflects downloads up to 13 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Mitra T(2017)Application-Specific ProcessorsHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_13-1(1-33)Online publication date: 8-Apr-2017
https://doi.org/10.1007/978-94-017-7358-4_13-1
Mitra T(2017)Application-Specific ProcessorsHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_13(377-409)Online publication date: 27-Sep-2017
https://doi.org/10.1007/978-94-017-7267-9_13
Zhong GVenkataramani VLiang YMitra TNiar S(2014)Design space exploration of multiple loops on FPGAs using high level synthesis2014 IEEE 32nd International Conference on Computer Design (ICCD)10.1109/ICCD.2014.6974719(456-463)Online publication date: Oct-2014
https://doi.org/10.1109/ICCD.2014.6974719
Yazdanbakhsh AKamal MFakhraie SAfzali-Kusha ASafari SPedram M(2014)Implementation-aware selection of the custom instruction set for extensible processorsMicroprocessors and Microsystems10.1016/j.micpro.2014.05.00738:7(681-691)Online publication date: Oct-2014
https://doi.org/10.1016/j.micpro.2014.05.007
Lu YZhou HHu A(2012)Efficient design space exploration for component-based system designProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429480(466-472)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1145/2429384.2429480
Bordoloi USuri BNunna SChakraborty SEles PPeng Z(2012)Customizing Instruction Set Extensible Reconfigurable Processors Using GPUsProceedings of the 2012 25th International Conference on VLSI Design10.1109/VLSID.2012.107(418-423)Online publication date: 7-Jan-2012
https://dl.acm.org/doi/10.1109/VLSID.2012.107
Garcia PGomes TSalgado FCabral JMonteiro JTavares A(2012)RAPTOR-DesignProceedings of the 2012 Brazilian Symposium on Computing System Engineering10.1109/SBESC.2012.55(188-191)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1109/SBESC.2012.55
Bordoloi UTanasa BTahoori MEles PPeng ZShazli SChakraborty S(2012)Reliability-Aware Instruction Set Customization for ASIPs with Hardened LogicProceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications10.1109/RTCSA.2012.28(164-173)Online publication date: 19-Aug-2012
https://dl.acm.org/doi/10.1109/RTCSA.2012.28
Salgado FGarcia PGomes TCabral JMonteiro JTavares AEkpanyapong M(2012)Exploring metrics tradeoffs in a multithreading extensible processor2012 IEEE International Symposium on Industrial Electronics10.1109/ISIE.2012.6237291(1375-1380)Online publication date: May-2012
https://doi.org/10.1109/ISIE.2012.6237291
Venkatesh GSampson JGoulding-Hotta NVenkata STaylor MSwanson SGaluzzi CCarro LMoshovos APrvulovic M(2011)QsCoresProceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/2155620.2155640(163-174)Online publication date: 3-Dec-2011
https://dl.acm.org/doi/10.1145/2155620.2155640
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents