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A commitment-based management strategy for the performance and reliability enhancement of flash-memory storage systems

Published: 26 July 2009 Publication History

Abstract

Cost has been a major driving force in the development of the flash memory technology, but has also introduced serious challenges on reliability and performance for future products. In this work, we propose a commitment-based management strategy to resolve the reliability problem of many flash-memory products. A three-level address translation architecture with an adaptive block mapping mechanism is proposed to accelerate the address translation process with a limited amount of the RAM usage. Parallelism of operations over multiple chips is also explored with the considerations of the write constraints of multi-level-cell flash memory chips.

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Cited By

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  • (2023)Retention-Aware Read Acceleration Strategy for LDPC-Based NAND Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328932842:12(4597-4605)Online publication date: Dec-2023
  • (2021)Enabling the Duo-phase Data Management to Realize Longevity Bit-alterable Flash MemoryIEEE Transactions on Computers10.1109/TC.2021.3116862(1-1)Online publication date: 2021
  • (2020)Energy-Efficient GPU L2 Cache Design Using Instruction-Level Data Locality SimilarityACM Transactions on Design Automation of Electronic Systems10.1145/340806025:6(1-18)Online publication date: 18-Aug-2020
  • Show More Cited By

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cover image ACM Conferences
DAC '09: Proceedings of the 46th Annual Design Automation Conference
July 2009
994 pages
ISBN:9781605584973
DOI:10.1145/1629911
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 26 July 2009

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Author Tags

  1. embedded systems
  2. flash memory
  3. performance
  4. reliability
  5. secondary storage

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DAC '09
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DAC '09: The 46th Annual Design Automation Conference 2009
July 26 - 31, 2009
California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all
  • (2023)Retention-Aware Read Acceleration Strategy for LDPC-Based NAND Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328932842:12(4597-4605)Online publication date: Dec-2023
  • (2021)Enabling the Duo-phase Data Management to Realize Longevity Bit-alterable Flash MemoryIEEE Transactions on Computers10.1109/TC.2021.3116862(1-1)Online publication date: 2021
  • (2020)Energy-Efficient GPU L2 Cache Design Using Instruction-Level Data Locality SimilarityACM Transactions on Design Automation of Electronic Systems10.1145/340806025:6(1-18)Online publication date: 18-Aug-2020
  • (2020)A Locality Optimizer for Loop-dominated Applications Based on Reuse Distance AnalysisACM Transactions on Design Automation of Electronic Systems10.1145/339818925:6(1-26)Online publication date: 2-Sep-2020
  • (2020)MNFTLACM Transactions on Design Automation of Electronic Systems10.1145/339803725:6(1-19)Online publication date: 12-Aug-2020
  • (2020)When Storage Response Time Catches Up With Overall Context Switch Overhead, What Is Next?IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.301232239:11(4266-4277)Online publication date: Nov-2020
  • (2016)Virtual Flash ChipsIEEE Transactions on Computers10.1109/TC.2015.250656965:9(2872-2883)Online publication date: 1-Sep-2016
  • (2016)Capacity-Independent Address Mapping for Flash Storage Devices with Explosively Growing CapacityIEEE Transactions on Computers10.1109/TC.2015.242870265:2(448-465)Online publication date: 1-Feb-2016
  • (2016)An Efficient Sudden-Power-Off-Recovery Design with Guaranteed Booting Time for Solid State Drives2016 IEEE 8th International Memory Workshop (IMW)10.1109/IMW.2016.7493565(1-4)Online publication date: May-2016
  • (2016)Multi-version checkpointing for flash file systems2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2016.7428051(436-443)Online publication date: Jan-2016
  • Show More Cited By

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