research-article

On soft error rate analysis of scaled CMOS designs: a statistical perspective

Authors:

Charles H.-P. Wen,

Jayanta BhadraAuthors Info & Claims

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

Pages 157 - 163

https://doi.org/10.1145/1687399.1687428

Published: 02 November 2009 Publication History

Abstract

This paper re-examines the soft error effect caused by cosmic radiation in sub 90nm technologies. Considering the impact of process variation, a number of statistical natures of transient faults are found more sophisticated than their static ones. We apply the state-of-the-art statistical learning algorithm to tackle the complexity of these natures and build compact yet accurate generation and propagation models for transient fault distributions. A statistical analysis framework for soft error rate (SER) is also proposed on the basis of these models. Experimental results show that the proposed framework can obtain improved SER estimation compared to the static approaches.

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Cited By

Qian JZhang CWu ZDing HLi L(2024)Efficient Topology Reconfiguration for NoC-Based Multiprocessors: A Greedy-Memetic AlgorithmJournal of Parallel and Distributed Computing10.1016/j.jpdc.2024.104904(104904)Online publication date: Apr-2024
https://doi.org/10.1016/j.jpdc.2024.104904
Choudhury MGao MVarna APeer EForte D(2023)Enhanced PATRON: Fault Injection and Power-aware FSM Encoding Through Linear ProgrammingACM Transactions on Design Automation of Electronic Systems10.1145/361166928:6(1-26)Online publication date: 3-Aug-2023
https://dl.acm.org/doi/10.1145/3611669
Choudhury MGao MTajik SForte D(2022)TAMED: Transitional Approaches for LFI Resilient State Machine Encoding2022 IEEE International Test Conference (ITC)10.1109/ITC50671.2022.00011(46-55)Online publication date: Sep-2022
https://doi.org/10.1109/ITC50671.2022.00011
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On soft error rate analysis of scaled CMOS designs: a statistical perspective

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cover image ACM Conferences

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

November 2009

803 pages

ISBN:9781605588001

DOI:10.1145/1687399

General Chair:
Jaijeet Roychowdhury
Univ. of California, Berkeley, Berkeley, California

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 02 November 2009

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November 2 - 5, 2009

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Cited By

Qian JZhang CWu ZDing HLi L(2024)Efficient Topology Reconfiguration for NoC-Based Multiprocessors: A Greedy-Memetic AlgorithmJournal of Parallel and Distributed Computing10.1016/j.jpdc.2024.104904(104904)Online publication date: Apr-2024
https://doi.org/10.1016/j.jpdc.2024.104904
Choudhury MGao MVarna APeer EForte D(2023)Enhanced PATRON: Fault Injection and Power-aware FSM Encoding Through Linear ProgrammingACM Transactions on Design Automation of Electronic Systems10.1145/361166928:6(1-26)Online publication date: 3-Aug-2023
https://dl.acm.org/doi/10.1145/3611669
Choudhury MGao MTajik SForte D(2022)TAMED: Transitional Approaches for LFI Resilient State Machine Encoding2022 IEEE International Test Conference (ITC)10.1109/ITC50671.2022.00011(46-55)Online publication date: Sep-2022
https://doi.org/10.1109/ITC50671.2022.00011
Ghavami BRaji MGhavami BRaji M(2020)Process Variation-Aware Soft Error Rate Estimation Method for Integrated CircuitsSoft Error Reliability of VLSI Circuits10.1007/978-3-030-51610-9_3(25-43)Online publication date: 14-Oct-2020
https://doi.org/10.1007/978-3-030-51610-9_3
Cao XXiao LLi JZhang RLiu SWang J(2019)A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs)IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283442538:6(1109-1122)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1109/TCAD.2018.2834425
Raji MGhavami B(2018)Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process VariationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.256956225:1(247-260)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2016.2569562
Raji MGhavami B(2018)A Fast Statistical Soft Error Rate Estimation Method for Nano-scale Combinational CircuitsJournal of Electronic Testing: Theory and Applications10.1007/s10836-016-5583-332:3(291-305)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1007/s10836-016-5583-3
Rohanipoor MGhavami BRaji M(2017)Soft error tolerant design of combinational circuits based on a local logic substitution schemeMicroelectronics Journal10.1016/j.mejo.2017.08.00667(143-154)Online publication date: Sep-2017
https://doi.org/10.1016/j.mejo.2017.08.006
Sabet MGhavami B(2016)Statistical soft error rate estimation of combinational circuits using Bayesian networksCOMPEL - The international journal for computation and mathematics in electrical and electronic engineering10.1108/COMPEL-09-2015-031735:5(1760-1773)Online publication date: 5-Sep-2016
https://doi.org/10.1108/COMPEL-09-2015-0317
Rezaei SMiremadi SAsadi HFazeli M(2014)Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gatesMicroelectronics Reliability10.1016/j.microrel.2014.03.00354:6-7(1412-1420)Online publication date: Jun-2014
https://doi.org/10.1016/j.microrel.2014.03.003
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