research-article

Binning optimization based on SSTA for transparently-latched circuits

Authors:

Xuan ZengAuthors Info & Claims

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

Pages 328 - 335

https://doi.org/10.1145/1687399.1687462

Published: 02 November 2009 Publication History

Abstract

With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transparent latches are widely used. In this paper, we formulate and solve the binning optimization problem that decides the bin boundaries and their testing order to maximize the benefit (considering the test cost) for a transparently-latched circuit. The problem is decomposed into three sub-problems which are solved sequentially. First, to compute the clock period distribution of the transparently-latched circuit, a sample-based SSTA approach is developed which is based on the generalized stochastic collocation method (gSCM) with Sparse Grid technique. The minimal clock period on each sample point is found by solving a minimal cycle ratio problem in the constraint graph. Second, a greedy algorithm is proposed to maximize the sales profit by iteratively assigning each boundary to its optimal position. Then, an optimal algorithm of O(n log n) runtime is used to generate the optimal testing order of bin boundaries to minimize the test cost, based on alphabetic tree. Experiments on all the ISCAS'89 sequential benchmarks with 65-nm technology show 6.69% profit improvement and 14.00% cost reduction in average. The results also demonstrate that the proposed SSTA method achieves an error of 0.70% and speedup of 110X in average compared with the Monte Carlo simulation.

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Cited By

Gong MZhou HLi LTao JZeng X(2019)Binning Optimization for Transparently-Latched CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.208187030:2(270-283)Online publication date: 4-Jan-2019
https://dl.acm.org/doi/10.1109/TCAD.2010.2081870
ZHOU XYANG FZHOU HGONG MZHU HZHANG YZENG X(2014)Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable BuffersIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E97.A.2227E97.A:11(2227-2235)Online publication date: 2014
https://doi.org/10.1587/transfun.E97.A.2227

Index Terms

Binning optimization based on SSTA for transparently-latched circuits
1. Applied computing
  1. Physical sciences and engineering
    1. Engineering

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cover image ACM Conferences

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

November 2009

803 pages

ISBN:9781605588001

DOI:10.1145/1687399

General Chair:
Jaijeet Roychowdhury
Univ. of California, Berkeley, Berkeley, California

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation
IEEE CAS
IEEE Council on Electronic Design Automation (CEDA)

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 November 2009

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Research-article

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Division of Computing and Communication Foundations
National major Science and Technology special project of China
Ministry of Science and Technology of the People's Republic of China
Ministry of Education of the People's Republic of China
National Natural Science Foundation of China

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ICCAD '09

Sponsor:

SIGDA

ICCAD '09: The International Conference on Computer-Aided Design

November 2 - 5, 2009

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Gong MZhou HLi LTao JZeng X(2019)Binning Optimization for Transparently-Latched CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.208187030:2(270-283)Online publication date: 4-Jan-2019
https://dl.acm.org/doi/10.1109/TCAD.2010.2081870
ZHOU XYANG FZHOU HGONG MZHU HZHANG YZENG X(2014)Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable BuffersIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E97.A.2227E97.A:11(2227-2235)Online publication date: 2014
https://doi.org/10.1587/transfun.E97.A.2227

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