research-article

Modeling of layout-dependent stress effect in CMOS design

Authors:

Yu CaoAuthors Info & Claims

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

Pages 513 - 520

https://doi.org/10.1145/1687399.1687496

Published: 02 November 2009 Publication History

Abstract

Strain technology has been successfully integrated into CMOS fabrication to improve carrier transport properties since 90nm node. Due to the non-uniform stress distribution in the channel, the enhancement in carrier mobility, velocity, and threshold voltage shift strongly depend on circuit layout, leading to systematic performance variations among transistors. A compact stress model that physically captures this behavior is essential to bridge the process technology with design optimization. In this paper, starting from the first principle, a new layout-dependent stress model is proposed as a function of layout, temperature, and other device parameters. Furthermore, a method of layout decomposition is developed to partition the layout into a set of simple patterns for efficient model extraction. These solutions significantly reduce the complexity in stress modeling and simulation. They are comprehensively validated by TCAD simulation and published Si-data, including the state-of-the-art strain technologies and the STI stress effect. By embedding them into circuit analysis, the interaction between layout and circuit performance is well benchmarked at 45nm node.

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Cited By

Kim SYang SLim HLee HJeon JChoi JKim J(2023)Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test CircuitsIEEE Access10.1109/ACCESS.2023.329234611(70691-70697)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3292346
Jeong CMyung SHuh IChoi BKim JJang HLee HPark DLee KJang WRyu JCha MChoe JShim MKim D(2021)Bridging TCAD and AI: Its Application to Semiconductor DesignIEEE Transactions on Electron Devices10.1109/TED.2021.309384468:11(5364-5371)Online publication date: Nov-2021
https://doi.org/10.1109/TED.2021.3093844
Shauly E(2018)Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design RulesJournal of Low Power Electronics and Applications10.3390/jlpea80200208:2(20)Online publication date: 14-Jun-2018
https://doi.org/10.3390/jlpea8020020
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Index Terms

Modeling of layout-dependent stress effect in CMOS design
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware

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cover image ACM Conferences

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

November 2009

803 pages

ISBN:9781605588001

DOI:10.1145/1687399

General Chair:
Jaijeet Roychowdhury
Univ. of California, Berkeley, Berkeley, California

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

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Published: 02 November 2009

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ICCAD '09: The International Conference on Computer-Aided Design

November 2 - 5, 2009

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Kim SYang SLim HLee HJeon JChoi JKim J(2023)Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test CircuitsIEEE Access10.1109/ACCESS.2023.329234611(70691-70697)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3292346
Jeong CMyung SHuh IChoi BKim JJang HLee HPark DLee KJang WRyu JCha MChoe JShim MKim D(2021)Bridging TCAD and AI: Its Application to Semiconductor DesignIEEE Transactions on Electron Devices10.1109/TED.2021.309384468:11(5364-5371)Online publication date: Nov-2021
https://doi.org/10.1109/TED.2021.3093844
Shauly E(2018)Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design RulesJournal of Low Power Electronics and Applications10.3390/jlpea80200208:2(20)Online publication date: 14-Jun-2018
https://doi.org/10.3390/jlpea8020020
Sharma AAlam NBulusu A(2018)Effective Drive Current for Near-Threshold CMOS Circuits’ Performance Evaluation: Modeling to Circuit Design TechniquesIEEE Transactions on Electron Devices10.1109/TED.2018.282534165:6(2413-2421)Online publication date: Jun-2018
https://doi.org/10.1109/TED.2018.2825341
Sharma AAlam NBulusu A(2018)UTBB FD-SOI Circuit Design using Multifinger Transistors: A Circuit-Device Interaction Perspective2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)10.1109/PRIME.2018.8430312(57-60)Online publication date: Jul-2018
https://doi.org/10.1109/PRIME.2018.8430312
Sharma AAlam NBulusu A(2017)Effective Current Model for Inverter-Transmission Gate Structure and Its Application in Circuit DesignIEEE Transactions on Electron Devices10.1109/TED.2017.274235864:10(4002-4010)Online publication date: Oct-2017
https://doi.org/10.1109/TED.2017.2742358
Ou HTseng KLiu JWu IChang Y(2016)Layout-Dependent Effects-Aware Analytical Analog PlacementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.250129335:8(1243-1254)Online publication date: 1-Aug-2016
https://dl.acm.org/doi/10.1109/TCAD.2015.2501293
Kaur BSharma AAlam NManhas SAnand B(2016)A variation aware timing model for a 2-input NAND gate and its use in sub-65nm CMOS standard cell characterizationMicroelectronics Journal10.1016/j.mejo.2016.03.01053(45-55)Online publication date: Jul-2016
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Ou HTseng KLiu JWu IChang Y(2015)Layout-dependent-effects-aware analytical analog placementProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744865(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744865
Sharma AUpadhyay PAnsar RLaxmi VBhargava LGaur MZwolinski M(2015)A framework for thermal aware reliability estimation in 2D NoC2015 19th International Symposium on VLSI Design and Test10.1109/ISVDAT.2015.7208063(1-6)Online publication date: Jun-2015
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