research-article

Hardware/software optimization of error detection implementation for real-time embedded systems

Authors:

Viacheslav IzosimovAuthors Info & Claims

CODES/ISSS '10: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Pages 41 - 50

https://doi.org/10.1145/1878961.1878970

Published: 24 October 2010 Publication History

Abstract

This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant real-time distributed embedded systems used for safety-critical applications. An application is modeled as a set of processes communicating by messages. Processes are mapped on computation nodes connected to the communication infrastructure. To provide resiliency against transient faults, efficient error detection and recovery techniques have to be employed. Our main focus in this paper is on the efficient implementation of the error detection mechanisms. We have developed techniques to optimize the hardware/software implementation of error detection, in order to minimize the global worst-case schedule length, while meeting the imposed hardware cost constraints and tolerating multiple transient faults. We present two design optimization algorithms which are able to find feasible solutions given a limited amount of resources: the first one assumes that, when implemented in hardware, error detection is deployed on static reconfigurable FPGAs, while the second one considers partial dynamic reconfiguration capabilities of the FPGAs.

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Cited By

Yuan BChen HYao X(2020)Toward Efficient Design Space Exploration for Fault-Tolerant Multiprocessor SystemsIEEE Transactions on Evolutionary Computation10.1109/TEVC.2019.291272624:1(157-169)Online publication date: Feb-2020
https://doi.org/10.1109/TEVC.2019.2912726
Donnarumma CBiondi ADe Rosa FDi Carlo S(2020)Integrating Online Safety-related Memory Tests in Multicore Real-Time Systems2020 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS49844.2020.00035(296-307)Online publication date: Dec-2020
https://doi.org/10.1109/RTSS49844.2020.00035
Yuan BLi BChen HZeng ZYao X(2019)Multi-objective redundancy hardening with optimal task mapping for independent tasks on multi-coresSoft Computing10.1007/s00500-019-03937-0Online publication date: 27-Mar-2019
https://doi.org/10.1007/s00500-019-03937-0
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Index Terms

Hardware/software optimization of error detection implementation for real-time embedded systems
1. Computer systems organization
2. Hardware
  1. Hardware test
  2. Robustness

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cover image ACM Conferences

CODES/ISSS '10: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

October 2010

348 pages

ISBN:9781605589053

DOI:10.1145/1878961

Program Chairs:
Tony Givargis
University of California, Irvine, CA
,
Adam Donlin
Xilinx, USA

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 24 October 2010

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Cited By

Yuan BChen HYao X(2020)Toward Efficient Design Space Exploration for Fault-Tolerant Multiprocessor SystemsIEEE Transactions on Evolutionary Computation10.1109/TEVC.2019.291272624:1(157-169)Online publication date: Feb-2020
https://doi.org/10.1109/TEVC.2019.2912726
Donnarumma CBiondi ADe Rosa FDi Carlo S(2020)Integrating Online Safety-related Memory Tests in Multicore Real-Time Systems2020 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS49844.2020.00035(296-307)Online publication date: Dec-2020
https://doi.org/10.1109/RTSS49844.2020.00035
Yuan BLi BChen HZeng ZYao X(2019)Multi-objective redundancy hardening with optimal task mapping for independent tasks on multi-coresSoft Computing10.1007/s00500-019-03937-0Online publication date: 27-Mar-2019
https://doi.org/10.1007/s00500-019-03937-0
Huang JBarner SRaabe ABuckl CKnoll A(2018)A framework for reliability-aware embedded system design on multiprocessor platformsMicroprocessors & Microsystems10.1016/j.micpro.2014.02.00738:6(539-551)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1016/j.micpro.2014.02.007
Namazi AAbdollahi MSafari SMohammadi S(2017)A Majority-Based Reliability-Aware Task Mapping in High-Performance Homogenous NoC ArchitecturesACM Transactions on Embedded Computing Systems10.1145/313127317:1(1-31)Online publication date: 6-Dec-2017
https://dl.acm.org/doi/10.1145/3131273
Namazi AAbdollahi MSafari SMohammadi S(2016)A Majority-Based Reliability-Aware Task-Mapping in High-Performance Homogenous NoC Architectures2016 Euromicro Conference on Digital System Design (DSD)10.1109/DSD.2016.28(479-486)Online publication date: Aug-2016
https://doi.org/10.1109/DSD.2016.28
Chen JShafique MMitra TReineke J(2014)Embedded software reliability for unreliable hardwareProceedings of the 14th International Conference on Embedded Software10.1145/2656045.2661649(1-1)Online publication date: 12-Oct-2014
https://dl.acm.org/doi/10.1145/2656045.2661649
Bolchini CMiele A(2013)Reliability-Driven System-Level Synthesis for Mixed-Critical Embedded SystemsIEEE Transactions on Computers10.1109/TC.2012.22662:12(2489-2502)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1109/TC.2012.226
Jiang KEles PPeng ZRosenstiel WMacii E(2012)Co-design techniques for distributed real-time embedded systems with communication security constraintsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492945(947-952)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492945
Huang JHuang KRaabe ABuckl CKnoll AGroeneveld PSciuto DHassoun S(2012)Towards fault-tolerant embedded systems with imperfect fault detectionProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228398(188-196)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228398
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