research-article

Iris: A hybrid nanophotonic network design for high-performance and low-power on-chip communication

Authors:

Moustafa Mohamed,

Alan Mickelson,

Manish VachharajaniAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 7, Issue 2

Article No.: 8, Pages 1 - 22

https://doi.org/10.1145/1970406.1970410

Published: 01 July 2011 Publication History

Abstract

On-chip communication, including short, often-multicast, latency-critical coherence and synchronization messages, and long, unicast, throughput-sensitive data transfers, limits the power efficiency and performance scalability of many-core chip-multiprocessor systems. This article analyzes on-chip communication challenges and studies the characteristics of existing electrical and emerging nanophotonic interconnect. Iris, a CMOS-compatible high-performance low-power nanophotonic on-chip network, is thus introduced. Iris's circuit-switched subnetwork supports throughput-sensitive data transfer. Iris's optical-antenna-array-based broadcast--multicast subnetwork optimizes latency-critical traffic and supports the path setup of circuit-switched communication. Overall, the proposed nanophotonic network design offers an on-chip communication backplane that is power efficient while demonstrating low latency and high throughput.

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De Magalhaes FNikdast MHessel FLiboiron-Ladouceur ONicolescu G(2021)HyCo: A Low-Latency Hybrid Control Plane for Optical Interconnection Networks2021 IEEE International Workshop on Rapid System Prototyping (RSP)10.1109/RSP53691.2021.9806198(50-56)Online publication date: 14-Oct-2021
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Yahya MWu NAli Z(2020)Reliability and Security Challenges in Electrical/Optical On-Chip Interconnects for IoT ApplicationsIoT Architectures, Models, and Platforms for Smart City Applications10.4018/978-1-7998-1253-1.ch011(218-246)Online publication date: 2020
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Alexoudi TTerzenidis NPitris SMoralis-Pegios MManiotis PVagionas CMitsolidou CMourgias-Alexandris GKanellos GMiliou AVyrsokinos KPleros N(2019)Optics in Computing: From Photonic Network-on-Chip to Chip-to-Chip Interconnects and Disintegrated ArchitecturesJournal of Lightwave Technology10.1109/JLT.2018.287599537:2(363-379)Online publication date: 15-Jan-2019
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Index Terms

Iris: A hybrid nanophotonic network design for high-performance and low-power on-chip communication
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Interconnection architectures

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cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 7, Issue 2

June 2011

123 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/1970406

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Copyright © 2011 ACM.

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Publication History

Published: 01 July 2011

Accepted: 01 March 2011

Revised: 01 January 2011

Received: 01 August 2010

Published in JETC Volume 7, Issue 2

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Cited By

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https://doi.org/10.1109/RSP53691.2021.9806198
Yahya MWu NAli Z(2020)Reliability and Security Challenges in Electrical/Optical On-Chip Interconnects for IoT ApplicationsIoT Architectures, Models, and Platforms for Smart City Applications10.4018/978-1-7998-1253-1.ch011(218-246)Online publication date: 2020
https://doi.org/10.4018/978-1-7998-1253-1.ch011
Alexoudi TTerzenidis NPitris SMoralis-Pegios MManiotis PVagionas CMitsolidou CMourgias-Alexandris GKanellos GMiliou AVyrsokinos KPleros N(2019)Optics in Computing: From Photonic Network-on-Chip to Chip-to-Chip Interconnects and Disintegrated ArchitecturesJournal of Lightwave Technology10.1109/JLT.2018.287599537:2(363-379)Online publication date: 15-Jan-2019
https://doi.org/10.1109/JLT.2018.2875995
Xiang DPan Q(2019)Low-power and high-performance adaptive routing in on-chip networksCCF Transactions on High Performance Computing10.1007/s42514-019-00009-5Online publication date: 2-Jul-2019
https://doi.org/10.1007/s42514-019-00009-5
Yahya MWu NAli ZKhizar Y(2019)Optical Versus Electrical: Performance Evaluation of Network On-Chip Topologies for UWASN Manycore ProcessorsWireless Personal Communications: An International Journal10.1007/s11277-019-06630-5116:2(963-991)Online publication date: 1-Aug-2019
https://dl.acm.org/doi/10.1007/s11277-019-06630-5
Yang YChen KGu HZhang BZhu L(2018)TAONoC: A Regular Passive Optical Network-on-Chip Architecture Based on Comb SwitchesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.2885141(1-10)Online publication date: 2018
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Yahya MWu NYan GYasir Y(2018)Review of Photonic and Hybrid On Chip Interconnects for MPSoCs in IoT Paradigm2018 21st Saudi Computer Society National Computer Conference (NCC)10.1109/NCG.2018.8593055(1-6)Online publication date: Apr-2018
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Temuçin Hİmre K(2018)Scheduling computation and communication on a software-defined photonic Network-on-Chip architecture for high-performance real-time systemsJournal of Systems Architecture10.1016/j.sysarc.2018.07.00790(54-71)Online publication date: Oct-2018
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Zhang BGu HWang KYang YTan W(2017)Low Polling Time TDM ONoC With Direction-Based Wavelength AssignmentJournal of Optical Communications and Networking10.1364/JOCN.9.0004799:6(479)Online publication date: 22-May-2017
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Werner SNavaridas JLuján M(2017)A Survey on Optical Network-on-Chip ArchitecturesACM Computing Surveys10.1145/313134650:6(1-37)Online publication date: 6-Dec-2017
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