Interconnect physical analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for cryptographic accelerators
Pages 225 - 232
Abstract
This paper introduces Interconnect Physical Analyser (IPAA) - a tool for the analysis and optimisation of SoC/NoC toplevel interconnect. IPAA extracts information from the IC router and power analysis tool after implementation. Combining information from both sources, the tool performs a wirelength-driven power analysis of toplevel interconnect in the design. A range of statistics for toplevel interconnect is reported and a set of plots is produced. Multiple designs can be analysed simultaneously, enabling comparison and optimisation. The tool is applied to the design of scalable, efficient bus-replacement Network-on-Chip interconnect for Public Key Cryptographic accelerators. IPAA analyses the physical effects of scaling the cryptographic accelerator's floorplan, the number of cores and the cryptographic wordlength. The tool's plots and reports highlight the efficiency and scalability of the bus replacement Network-on-Chip and help guide the optimisation of the design.
References
[1]
N. Magen, A. Kolodny, U. Weiser, and N. Shamir, "Interconnect-power dissipation in a microprocessor," SLIP '04: Proceedings of the 2004 international workshop on System level interconnect prediction, Feb 2004.
[2]
International Technology Roadmap for Semiconductors - 2005 Edition, "Interconnect," Dec 2006. http://www.itrs.net/Links/2005ITRS/Interconnect2005.pdf.
[3]
R. Nagpal, A. Madan, A. Bhardwaj, and Y. Srikant, "INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations," Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, 2007.
[4]
V. Venkatraman, A. Laffely, J. Jang, H. Kukkamalla, Z. Zhu, and W. Burleson, "NoCIC: a SPICE-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods," SLIP '04: Proceedings of the 2004 international workshop on System level interconnect prediction, Feb 2004.
[5]
A. Kahng, B. Li, L.-S. Peh, and K. Samadi, "ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration," Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09., pp. 423--428, 2009.
[6]
F. Angiolini, P. Meloni, S. Carta, and L. Raffo, "A layout-aware analysis of networks-on-chip and traditional interconnects for MPSoCs," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Jan 2007.
[7]
A. Pullini, F. Angiolini, S. Murali, D. Atienza, G. D. Micheli, and L. Benini, "Bringing NoCs to 65 nm," Micro, IEEE, vol. 27, no. 5, pp. 75--85, 2007.
[8]
T. English, E. M. Popovici, M. Keller, and W. Marnane, "Network-on-Chip interconnect for pairing-based cryptographic IP cores," Journal of Systems Architecture, vol. 57, pp. 95--108, Nov 2011.
[9]
J.-L. Beuchat, H. Doi, K. Fujita, A. Inomata, P. Ith, A. Kanaoka, M. Katouno, M. Mambo, E. Okamoto, and T. Okamoto, "FPGA and ASIC implementations of the ηT pairing in characteristic three," Computers & Electrical Engineering, vol. 36, no. 1, pp. 73--87, 2010.
[10]
A. Satoh and K. Takano, "A scalable dual-field elliptic curve cryptographic processor," IEEE Transactions on Computers, vol. 52, no. 4, pp. 449--460, 2003.
[11]
M. Sun, C. Su, C. Huang, and C. Wu, "Design of a scalable RSA and ECC crypto-processor," Proceedings of the 2003 Asia and South Pacific Design Automation Conference, pp. 495--498, 2003.
[12]
M. Keller, R. Ronan, W. Marnane, and C. Murphy, "Hardware architectures for the Tate pairing over GF(2 m)," Computers & Electrical Engineering, vol. 33, pp. 392--406, Jan 2007.
Index Terms
- Interconnect physical analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for cryptographic accelerators
Recommendations
Interconnect Physical Optimization
ISPD '18: Proceedings of the 2018 International Symposium on Physical DesignThe SoC Interconnect is one of the most important IPs in modern chips as it is the logical and physical instantiation of an SoC architecture and carries virtually all the SoC data. Interconnect IPs have to carry non-coherent, cache coherent, subsystem ...
Network-on-Chip interconnect for pairing-based cryptographic IP cores
On-chip data traffic in cryptographic circuits often consists of very long words or large groups of smaller words exchanged between processing elements. The resulting wide cross-chip buses exhibit power, congestion and scalability problems. In this ...
System level interconnect design for network-on-chip using interconnect IPs
SLIP '03: Proceedings of the 2003 international workshop on System-level interconnect predictionAs technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a Network-on-Chip (NoC) architecture was proposed by ...
Comments
Information & Contributors
Information
Published In
May 2011
282 pages
ISBN:9781450307208
DOI:10.1145/1999946
- General Chairs:
- Radu Marculescu,
- Mike Kishinevsky,
- Program Chairs:
- Ran Ginosar,
- Karam S. Chatha
Copyright © 2011 ACM.
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]
Sponsors
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 01 May 2011
Check for updates
Author Tags
Qualifiers
- Research-article
Conference
Acceptance Rates
Overall Acceptance Rate 14 of 44 submissions, 32%
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 66Total Downloads
- Downloads (Last 12 months)1
- Downloads (Last 6 weeks)0
Reflects downloads up to 08 Feb 2025
Other Metrics
Citations
View Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in