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TIERS: Topology independent pipelined routing and scheduling for VirtualWire compilation

Authors:

Charles Selvidge,

Anant Agarwal,

Matt Dahl, and

Jonathan BabbAuthors Info & Claims

FPGA '95: Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

February 1995

Pages 25 - 31

https://doi.org/10.1145/201310.201314

Published: 15 February 1995 Publication History

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Abstract

TIERS is a new pipelined routing and scheduling algorithm implemented in a complete VirtualWire^TM compilation and synthesis system. TIERS is described and compared to prior work both analytically and quantitatively. TIERS improves system speed by as much as a factor of 2.5 over prior work. TIERS routing results for both Altera and Xilinx based FPGA systems are provided.

References

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J. Babb et al. Virtual Wires: Overcoming Pin Limitation in FPGA-based Logic Emulators. In Proceedings, IEEE Workshop on FPGA-based Custom Computing MAchines, pages 142-151, Napa, CA April 1993. IEEE. Also as MIT/LCS TM-491, January 1993.

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M. Dahl et al. Emulation of the Sparcle Microprocessor with the MIT Virtual Wires Emulation System. In Proceedings, IEEE Workshop on FPGAs For Custom Computing Machines, pages14 -22, Napa Valley California, April 1994. IEEE Computer Society, IEEE Computer Society Press.

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R. Tessier et al. The Virtual Wires Emulation System: A Gate-Efficient ASIC Prototyping Environment. Submitted to 1994 ACM International Workshop on Field-Programmable Gate Arrays, Berkeley, CA, February 1994, ACM.

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Cited By

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Wijtvliet MWaeijen LCorporaal H(2016)Coarse grained reconfigurable architectures in the past 25 years: Overview and classification2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)10.1109/SAMOS.2016.7818353(235-244)Online publication date: Jul-2016
https://doi.org/10.1109/SAMOS.2016.7818353
Fleming KAdler MPellauer MParashar AMithal AEmer JCompton KHutchings B(2012)Leveraging latency-insensitivity to ease multiple FPGA designProceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays10.1145/2145694.2145725(175-184)Online publication date: 22-Feb-2012
https://dl.acm.org/doi/10.1145/2145694.2145725
Babb JTessier RDahl MHanono SHoki DAgarwal A(2006)Logic emulation with virtual wiresIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.64061916:6(609-626)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.640619
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Index Terms

TIERS: Topology independent pipelined routing and scheduling for VirtualWire compilation
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing
  2. Very large scale integration design
    1. Application-specific VLSI designs
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory
      1. Paths and connectivity problems

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Published In

FPGA '95: Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

February 1995

174 pages

ISBN:089791743X

DOI:10.1145/201310

Chairmen:
Pak K. Chan
Univ. of California at Santa Cruz, Santa Cruz
,
Jonathan Rose
Univ. of Toronto, Toronto, Ont., Canada

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 15 February 1995

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FPGA95

Sponsor:

SIGDA

FPGA95: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 12 - 14, 1995

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

View all

Wijtvliet MWaeijen LCorporaal H(2016)Coarse grained reconfigurable architectures in the past 25 years: Overview and classification2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)10.1109/SAMOS.2016.7818353(235-244)Online publication date: Jul-2016
https://doi.org/10.1109/SAMOS.2016.7818353
Fleming KAdler MPellauer MParashar AMithal AEmer JCompton KHutchings B(2012)Leveraging latency-insensitivity to ease multiple FPGA designProceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays10.1145/2145694.2145725(175-184)Online publication date: 22-Feb-2012
https://dl.acm.org/doi/10.1145/2145694.2145725
Babb JTessier RDahl MHanono SHoki DAgarwal A(2006)Logic emulation with virtual wiresIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.64061916:6(609-626)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.640619
Kudlugi MSelvidge CTessier RErnst R(2001)Static scheduling of multi-domain memories for functional verificationProceedings of the 2001 IEEE/ACM international conference on Computer-aided design10.5555/603095.603097(2-9)Online publication date: 4-Nov-2001
https://dl.acm.org/doi/10.5555/603095.603097
Vemuri RGovindarajan SOuaiss IKaul MSrinivasan VRadhakrishnan SSundaraman SGanesan SPandey ALakshmikanthan P(2001)Automated design synthesis and partitioning for adaptive reconfigurable hardwareHardware implementation of intelligent systems10.5555/570780.570781(3-52)Online publication date: 1-Jan-2001
https://dl.acm.org/doi/10.5555/570780.570781
Babb JTessier RDahl MHanono SHoki DAgarwal A(2001)Logic emulation with virtual wiresReadings in hardware/software co-design10.5555/567003.567060(625-642)Online publication date: 1-Jun-2001
https://dl.acm.org/doi/10.5555/567003.567060
Kudlugi MSelvidge CTessier RRabaey J(2001)Static schedluing of multiple asynchronous domains for functional verificationProceedings of the 38th annual Design Automation Conference10.1145/378239.379040(647-652)Online publication date: 22-Jun-2001
https://dl.acm.org/doi/10.1145/378239.379040
Kudlugi MSelvidge CTessier R(2001)Static scheduling of multi-domain memories for functional verificationIEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281)10.1109/ICCAD.2001.968590(2-9)Online publication date: 2001
https://doi.org/10.1109/ICCAD.2001.968590
Tessier R(1999)Incremental compilation for logic emulationProceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype (Cat. No.PR00246)10.1109/IWRSP.1999.779059(236-241)Online publication date: 1999
https://doi.org/10.1109/IWRSP.1999.779059

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