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Multiple FPGA partitioning with performance optimization

Authors:

Kalapi Roy-Neogi,

Carl SechenAuthors Info & Claims

FPGA '95: Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

Pages 146 - 152

https://doi.org/10.1145/201310.201333

Published: 15 February 1995 Publication History

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Kiełbik RRudnicki KMudza ZJung J(2020)Methodology of Firmware Development for ARUZ—An FPGA-Based HPC SystemElectronics10.3390/electronics90914829:9(1482)Online publication date: 10-Sep-2020
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Mao FZhang WFeng BHe BMa YCoskun AMargala MBehjat LHan J(2016)Modular Placement for Interposer based Multi-FPGA SystemsProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2903025(93-98)Online publication date: 18-May-2016
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Nunna KMehdipour FMurakami K(2014)3D FPGA versus multiple FPGA systemProceedings of the Twelfth Australasian Symposium on Parallel and Distributed Computing - Volume 15210.5555/2667672.2667677(37-43)Online publication date: 20-Jan-2014
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Multiple FPGA partitioning with performance optimization

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Published In

FPGA '95: Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

February 1995

174 pages

ISBN:089791743X

DOI:10.1145/201310

Chairmen:
Pak K. Chan
Univ. of California at Santa Cruz, Santa Cruz
,
Jonathan Rose
Univ. of Toronto, Toronto, Ont., Canada

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 15 February 1995

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FPGA95

Sponsor:

SIGDA

FPGA95: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 12 - 14, 1995

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

View all

Kiełbik RRudnicki KMudza ZJung J(2020)Methodology of Firmware Development for ARUZ—An FPGA-Based HPC SystemElectronics10.3390/electronics90914829:9(1482)Online publication date: 10-Sep-2020
https://doi.org/10.3390/electronics9091482
Mao FZhang WFeng BHe BMa YCoskun AMargala MBehjat LHan J(2016)Modular Placement for Interposer based Multi-FPGA SystemsProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2903025(93-98)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2902961.2903025
Nunna KMehdipour FMurakami K(2014)3D FPGA versus multiple FPGA systemProceedings of the Twelfth Australasian Symposium on Parallel and Distributed Computing - Volume 15210.5555/2667672.2667677(37-43)Online publication date: 20-Jan-2014
https://dl.acm.org/doi/10.5555/2667672.2667677
Lin P(2012)Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flatteningProceedings of the 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)10.1109/ICCD.2012.6378634(153-158)Online publication date: 30-Sep-2012
https://dl.acm.org/doi/10.1109/ICCD.2012.6378634
Bolchini CSandionigi C(2011)A Reliability-Aware Partitioner for Multi-FPGA PlatformsProceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems10.1109/DFT.2011.20(34-40)Online publication date: 3-Oct-2011
https://dl.acm.org/doi/10.1109/DFT.2011.20
Khodja DKheldoun ARefoufi L(2010)Sigmoid function approximation for ANN implementation in FPGA devicesProceedings of the 9th WSEAS international conference on Circuits, systems, electronics, control & signal processing10.5555/1938801.1938822(112-116)Online publication date: 29-Dec-2010
https://dl.acm.org/doi/10.5555/1938801.1938822
Liu HWong D(2006)Network-flow-based multiway partitioning with area and pin constraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.67363217:1(50-59)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.673632
Fang WWu A(2006)A hierarchical functional structuring and partitioning approach for multiple-FPGA implementationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.66268016:10(1188-1195)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.662680
Kwon YKyung C(2005)ATOMiIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2005.85011713:7(861-864)Online publication date: 1-Jul-2005
https://dl.acm.org/doi/10.1109/TVLSI.2005.850117
Mak WSapatnekar SWiesel M(2001)Min-cut partitioning with functional replication for technology mapped circuits using minimum area overheadProceedings of the 2001 international symposium on Physical design10.1145/369691.369746(100-105)Online publication date: 1-Apr-2001
https://dl.acm.org/doi/10.1145/369691.369746
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