Article

Free access

Effects of FPGA architecture on FPGA routing

Author:

Stephen TrimbergerAuthors Info & Claims

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Pages 574 - 578

https://doi.org/10.1145/217474.217592

Published: 01 January 1995 Publication History

PDF eReader

References

[1]

S. Brown, et. al., Field-Programmable Gate Arrays, Kluwer Academic Publishers, 1992.

Digital Library

Google Scholar

[2]

A. E1 Gamal, J. Greene, V. Roychowdhury. "Segmented Channel Routing is Nearly as Efficient as Channel Routing (and Just as Hard)," Proceedings. VLSI Conference, Santa Cruz, CA, March 1991.

Digital Library

Google Scholar

[3]

A. E1 Gamal, "Two-Dimensional Stochastic Model for Interconnection in Master Slice Integrated Circuits," IEEE Transactions on Circuits and Systems, vol. CAS-28, no. 2, February 1981.

Google Scholar

[4]

J. Frankle, "Iterative and Adaptive Slack Allocation for Performance-driven Layout and FPGA Routing", Proceedings of the 29th Design Automation Conference, 1992.

Digital Library

Google Scholar

[5]

J. Greene, V. Roychowdhury, S. Kaptanoglu, A. E1 Gamal, "Segmented Channel Routing," Proceedings of the 27th Design Automation Conference, 1990.

Digital Library

Google Scholar

[6]

W.R. Heller, et. al., "Prediction of Wiring Space Requirements for LSI," Journal of Design Automation and Fault Tolerant Computing, May 1978.

Google Scholar

[7]

E Penfield, Jr., J. Rubenstein, "Signal Delay in RC Tree Networks," Proceedings of the 18th Design Automation Conference, 1981.

Digital Library

Google Scholar

[8]

S. Trimberger, ed., Field-Programmable Gate Array Technology, Kluwer Academic Publishers, 1994.

Digital Library

Google Scholar

[9]

Y. Wu and M. Marek-Sadowska, "Graph Based Analysis of FPGA Routing", Proceedings of Euro-DA C, IEEE, 1993.

Crossref

Google Scholar

Cited By

View all

Mukherjee SRoy S(2016)Nearly-2-SAT Solutions for Segmented-Channel RoutingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.244695035:1(128-140)Online publication date: Jan-2016
https://doi.org/10.1109/TCAD.2015.2446950
He TZhang FBhunia SFeng P(2015)Silicon Carbide (SiC) Nanoelectromechanical Antifuse for Ultralow-Power One-Time-Programmable (OTP) FPGA InterconnectsIEEE Journal of the Electron Devices Society10.1109/JEDS.2015.24213013:4(323-335)Online publication date: Jul-2015
https://doi.org/10.1109/JEDS.2015.2421301
Ayorinde OHe Qi Yu Huang Calhoun B(2015)Using island-style bi-directional intra-CLB routing in low-power FPGAs2015 25th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2015.7293945(1-7)Online publication date: Sep-2015
https://doi.org/10.1109/FPL.2015.7293945
Show More Cited By

Index Terms

Effects of FPGA architecture on FPGA routing
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing
  2. Very large scale integration design
    1. Application-specific VLSI designs

Recommendations

Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow
Special Section on Field Programmable Logic and Applications 2015 and Regular Papers

In this article, we consider implementing field-programmable gate arrays (FPGAs) using a standard cell design methodology and present a framework for the automated generation of synthesizable FPGA fabrics. The open-source Verilog-to-Routing (VTR) FPGA ...
An Asynchronous Dataflow FPGA Architecture

We discuss the design of a high-performance field programmable gate array (FPGA) architecture that efficiently prototypes asynchronous (clockless) logic. In this FPGA architecture, low-level application logic is described using asynchronous dataflow ...
FPGA Architecture

Comments

Information & Contributors

Information

Published In

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

January 1995

760 pages

ISBN:0897917251

DOI:10.1145/217474

Chairman:
Bryan T. Preas
Xerox Parc, Palo Alto, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 January 1995

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

DAC95

Sponsor:

EDAC
SIGDA

DAC95: The 32nd Design Automation Conference

June 12 - 16, 1995

California, San Francisco, USA

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

11
Total Citations
View Citations
1,434
Total Downloads

Downloads (Last 12 months)166
Downloads (Last 6 weeks)21

Reflects downloads up to 16 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Mukherjee SRoy S(2016)Nearly-2-SAT Solutions for Segmented-Channel RoutingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.244695035:1(128-140)Online publication date: Jan-2016
https://doi.org/10.1109/TCAD.2015.2446950
He TZhang FBhunia SFeng P(2015)Silicon Carbide (SiC) Nanoelectromechanical Antifuse for Ultralow-Power One-Time-Programmable (OTP) FPGA InterconnectsIEEE Journal of the Electron Devices Society10.1109/JEDS.2015.24213013:4(323-335)Online publication date: Jul-2015
https://doi.org/10.1109/JEDS.2015.2421301
Ayorinde OHe Qi Yu Huang Calhoun B(2015)Using island-style bi-directional intra-CLB routing in low-power FPGAs2015 25th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2015.7293945(1-7)Online publication date: Sep-2015
https://doi.org/10.1109/FPL.2015.7293945
Xu LShi W(2014)Removing the Root of TrustProceedings of the 2014 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2014.49(160-165)Online publication date: 9-Jul-2014
https://dl.acm.org/doi/10.1109/ISVLSI.2014.49
Hsieh JChang YLee W(2011)An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAsProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950944(661-667)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950944
Hsieh JChang YLee W(2011)An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAs16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)10.1109/ASPDAC.2011.5722270(661-667)Online publication date: Jan-2011
https://doi.org/10.1109/ASPDAC.2011.5722270
Tatas KSiozios KSoudris D(2007)A Survey of Existing Fine-Grain Reconfigurable Architectures and CAD toolsFine- and Coarse-Grain Reconfigurable Computing10.1007/978-1-4020-6505-7_1(3-87)Online publication date: 2007
https://doi.org/10.1007/978-1-4020-6505-7_1
Fei He William N. N. Hung Xiaoyu Song Ming Gu Jiaguang Sun (2005)Segment Channel Routing with Pin Rearrangements via Satisfiability2005 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2005.1466068(6248-6251)Online publication date: 2005
https://doi.org/10.1109/ISCAS.2005.1466068
Alexander MKahng ASarrafzadeh M(1997)Power optimization for FPGA look-up tablesProceedings of the 1997 international symposium on Physical design10.1145/267665.267707(156-162)Online publication date: 1-Apr-1997
https://dl.acm.org/doi/10.1145/267665.267707
Yao-Wen Chang Wong DWong C(1995)FPGA global routing based on a new congestion metricProceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors10.1109/ICCD.1995.528836(372-378)Online publication date: 1995
https://doi.org/10.1109/ICCD.1995.528836
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow

An Asynchronous Dataflow FPGA Architecture

FPGA Architecture