research-article

Synchronization scheme for brick-based rotary oscillator arrays

Authors:

Ying Teng,

Baris TaskinAuthors Info & Claims

GLSVLSI '12: Proceedings of the great lakes symposium on VLSI

Pages 117 - 122

https://doi.org/10.1145/2206781.2206812

Published: 03 May 2012 Publication History

Get Access

Abstract

In this paper, a brick-based rotary oscillator array (ROA) synchronization scheme is proposed, which directs all the rotary traveling wave oscillators (RTWOs) in the ROA to rotate in a pre-determined direction. This synchronization scheme increases the speed of the ROA synchronization process by eliminating the repetitive start-up trials due to start-ups from incorrect points on the oscillatory array. Simulation results confirm the effectiveness of the ROA synchronization scheme. Furthermore, the synchronization scheme is applied to an ROA-based clock generation and distribution network designed for an ISPD 10 clock benchmark in order to demonstrate its application at a larger scale.

References

[1]

W. Andress and D. Ham. Standing wave oscillators utilizing wave-adaptive tapered transmission lines. IEEE Journal of Solid-State Circuits, 40(3):638--651, March 2005.

Crossref

Google Scholar

[2]

S. Chan, P. Restle, K. Shepard, N. James, and R. Franch. A 4.6GHz resonant global clock distribution network. In IEEE International Solid-State Circuits Conference (ISSCC) Proceedings, pages 342--343, Febrary 2004.

Crossref

Google Scholar

[3]

V. Chi. Salphasic distribution of clock signals for synchronous systems. IEEE Trans. Comput., 43(5):597--602, May 1994.

Digital Library

Google Scholar

[4]

V. Cordero and S. Khatri. Clock distribution scheme using coplanar transmission lines. In Design, Automation and Test in Europe (DATE) Proceedings, pages 985--990, March 2008.

Digital Library

Google Scholar

[5]

A. Drake, K. Nowka, T. Nguyen, J. Burns, and R. Brown. Resonant clocking using distributed parasitic capacitance. IEEE Journal of Solid-State Circuits, 39(9):1520--1528, September 2004.

Crossref

Google Scholar

[6]

M. Edahiro. A clustering-based optimization algorithm in zero-skew routings. In ACM/IEEE Design Automation Conference (DAC) Proceedings, pages 612--616, June 1993.

Digital Library

Google Scholar

[7]

X. Hu and M. Guthaus. Distributed resonant clock grid synthesis (ROCKS). In ACM/IEEE Design Automation Conference (DAC) Proceedings, pages 516--521, June 2011.

Digital Library

Google Scholar

[8]

J. Lu, V. Honkote, X. Chen, and B. Taskin. Steiner tree based rotary clock routing with bounded skew and capacitive load balancing. In Design, Automation and Test in Europe (DATE) Proceedings, pages 455--460, March 2011.

Google Scholar

[9]

R.-S.Tsay. Exact zero skew. In IEEE International Conference on Computer-Aided Design (ICCAD) Proceedings, pages 336--339, November 1991.

Crossref

Google Scholar

[10]

K. Takinami, R. Walsworth, S. Osman, and S. Beccue. Phase-noise analysis in rotary traveling-wave oscillators using simple physical model. IEEE Trans. Microwave Theory Tech., 58(6):1465--1474, June 2010.

Crossref

Google Scholar

[11]

Y. Teng, J. Lu, and B. Taskin. Roa-brick topology for rotary resonant clocks. In IEEE International Conference on Computer Design (ICCD) Proceedings, pages 273--278, October 2011.

Digital Library

Google Scholar

[12]

V.Honkote and B.Taskin. Skew-aware capacitive load balancing for low-power zero clock skew rotary oscillatory array. In IEEE International Conference on Computer Design (ICCD) Proceedings, pages 209--214, October 2010.

Crossref

Google Scholar

[13]

J. Wood, T. Edwards, and S. Lipa. Rotary traveling-wave oscillator arrays: A new clock technology. IEEE Journal of Solid-State Circuits, 36(11):1654--1665, November 2001.

Crossref

Google Scholar

[14]

Y. Zhang, J. Buckwalter, and C. Cheng. On-chip global clock distribution using directional rotary traveling-wave oscillator. In IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Proceedings, pages 251--254, October 2009.

Crossref

Google Scholar

Cited By

View all

Kuttappa RTaskin BHonkote VYada SSundaram JKurian DKarnik TSrinivasan A(2022)Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer2022 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS48785.2022.9937877(692-696)Online publication date: 28-May-2022
https://doi.org/10.1109/ISCAS48785.2022.9937877
Kuttappa RTaskin B(2022)A 0.45 pJ/bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators2022 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS48785.2022.9937492(687-691)Online publication date: 28-May-2022
https://doi.org/10.1109/ISCAS48785.2022.9937492
Kuttappa RBalaji APano VTaskin BMahmoodi H(2019)RotaSYN: Rotary Traveling Wave Oscillator SYNthesizerIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2019.289681566:7(2685-2698)Online publication date: Jul-2019
https://doi.org/10.1109/TCSI.2019.2896815
Show More Cited By

Index Terms

Synchronization scheme for brick-based rotary oscillator arrays
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing
  2. Hardware validation
    1. Functional verification
      1. Simulation and emulation

Recommendations

Skew-bounded low swing clock tree optimization
GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

This paper introduces a methodology that optimizes the performance of a low swing clock tree under a skew bound. Low-swing clock trees are preferred for a reduction in the clock switching power, with an expected trade-off in clock slew and skew. In this ...
Flip-flop energy/performance versus clock slope and impact on the clock network design

In this paper, the influence of the clock slope on the speed of various classes of flip-flops (FFs) and on the overall energy dissipation of both FFs and clock domain buffers is analyzed. Analysis shows that an optimum clock slope exists, which ...
Design of rotary clock based circuits
DAC '07: Proceedings of the 44th annual Design Automation Conference

Rotary clock technique has been shown to reduce the power dissipation of clock distribution by up to 80%. However, to our knowledge, no practical digital synchronous circuit has been designed that utilizes the rotary technique due to the multi-phase ...

Comments

Information & Contributors

Information

Published In

GLSVLSI '12: Proceedings of the great lakes symposium on VLSI

May 2012

388 pages

ISBN:9781450312448

DOI:10.1145/2206781

General Chairs:
Erik Brunvard
University of Utah, USA
,
Ken Stevens
University of Utah, USA
,
Program Chairs:
Joseph R. Cavallaro
Rice University, USA
,
Tong Zhang
Rensselaer Polytechnic Institute, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 May 2012

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

GLSVLSI '12

Sponsor:

SIGDA

GLSVLSI '12: Great Lakes Symposium on VLSI 2012

May 3 - 4, 2012

Utah, Salt Lake City, USA

Acceptance Rates

Overall Acceptance Rate 312 of 1,156 submissions, 27%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

8
Total Citations
View Citations
112
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)0

Reflects downloads up to 27 Jul 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Kuttappa RTaskin BHonkote VYada SSundaram JKurian DKarnik TSrinivasan A(2022)Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer2022 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS48785.2022.9937877(692-696)Online publication date: 28-May-2022
https://doi.org/10.1109/ISCAS48785.2022.9937877
Kuttappa RTaskin B(2022)A 0.45 pJ/bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators2022 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS48785.2022.9937492(687-691)Online publication date: 28-May-2022
https://doi.org/10.1109/ISCAS48785.2022.9937492
Kuttappa RBalaji APano VTaskin BMahmoodi H(2019)RotaSYN: Rotary Traveling Wave Oscillator SYNthesizerIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2019.289681566:7(2685-2698)Online publication date: Jul-2019
https://doi.org/10.1109/TCSI.2019.2896815
Teng YTaskin B(2015)ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.238583523:11(2519-2530)Online publication date: Nov-2015
https://doi.org/10.1109/TVLSI.2014.2385835
Teng YTaskin BMacii E(2013)Sparse-rotary oscillator array (SROA) design for power and skew reductionProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485584(1229-1234)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485584
Teng YTaskin BAyala JJones AMadden PCoskun A(2013)Rotary traveling wave oscillator frequency division at nanoscale technologiesProceedings of the 23rd ACM international conference on Great lakes symposium on VLSI10.1145/2483028.2483137(349-350)Online publication date: 2-May-2013
https://dl.acm.org/doi/10.1145/2483028.2483137
Teng YTaskin B(2013)Resonant frequency divider design methodology for dynamic frequency scaling2013 IEEE 31st International Conference on Computer Design (ICCD)10.1109/ICCD.2013.6657087(479-482)Online publication date: Oct-2013
https://doi.org/10.1109/ICCD.2013.6657087
Guthaus MTaskin BHu A(2012)High-performance, low-power resonant clockingProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429545(742-745)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1145/2429384.2429545

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Skew-bounded low swing clock tree optimization

Flip-flop energy/performance versus clock slope and impact on the clock network design

Design of rotary clock based circuits