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Identifying sequential redundancies without search

Authors:

Mahesh A. Iyer,

David E. Long,

Miron AbramoviciAuthors Info & Claims

DAC '96: Proceedings of the 33rd annual Design Automation Conference

Pages 457 - 462

https://doi.org/10.1145/240518.240605

Published: 01 June 1996 Publication History

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Cited By

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Pomeranz I(2022)Efficient Identification of Undetectable Two-Cycle Gate-Exhaustive FaultsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.306276741:3(776-783)Online publication date: Mar-2022
https://doi.org/10.1109/TCAD.2021.3062767
Hosokawa TNiseki MYoshimura MYamazaki HArai MYotsuyanagi HHashizume M(2018)A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)10.1109/IOLTS.2018.8474268(43-46)Online publication date: Jul-2018
https://doi.org/10.1109/IOLTS.2018.8474268
Viilukas TKarputkin ARaik JJenihhin MUbar RFujiwara H(2012)Identifying Untestable Faults in Sequential Circuits Using Test Path ConstraintsJournal of Electronic Testing: Theory and Applications10.1007/s10836-012-5312-528:4(511-521)Online publication date: 1-Aug-2012
https://dl.acm.org/doi/10.1007/s10836-012-5312-5
Show More Cited By

Index Terms

Identifying sequential redundancies without search
1. Computer systems organization
  1. Dependable and fault-tolerant systems and networks
    1. Redundancy
2. Hardware
  1. Robustness
    1. Fault tolerance
      1. Redundancy

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Published In

DAC '96: Proceedings of the 33rd annual Design Automation Conference

June 1996

839 pages

ISBN:0897917790

DOI:10.1145/240518

Chairmen:
Thomas P. Pennino
Bell Labs, Holmdel, NJ
,
Ellen J. Yoffa
IBM Corp., Yorktown Heights, NY

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1996

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Sponsor:

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DAC96: The 33rd Design Automation Conference

June 3 - 7, 1996

Nevada, Las Vegas, USA

Acceptance Rates

DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Pomeranz I(2022)Efficient Identification of Undetectable Two-Cycle Gate-Exhaustive FaultsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.306276741:3(776-783)Online publication date: Mar-2022
https://doi.org/10.1109/TCAD.2021.3062767
Hosokawa TNiseki MYoshimura MYamazaki HArai MYotsuyanagi HHashizume M(2018)A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)10.1109/IOLTS.2018.8474268(43-46)Online publication date: Jul-2018
https://doi.org/10.1109/IOLTS.2018.8474268
Viilukas TKarputkin ARaik JJenihhin MUbar RFujiwara H(2012)Identifying Untestable Faults in Sequential Circuits Using Test Path ConstraintsJournal of Electronic Testing: Theory and Applications10.1007/s10836-012-5312-528:4(511-521)Online publication date: 1-Aug-2012
https://dl.acm.org/doi/10.1007/s10836-012-5312-5
Savoj HBerthelot DMishchenko ABrayton RBloem RSharygina N(2010)Combinational techniques for sequential equivalence checkingProceedings of the 2010 Conference on Formal Methods in Computer-Aided Design10.5555/1998496.1998524(145-150)Online publication date: 20-Oct-2010
https://dl.acm.org/doi/10.5555/1998496.1998524
Pomeranz IReddy SWakabayashi K(2009)Dynamic test compaction for a random test generation procedure with input cube avoidanceProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509786(672-677)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509786
Pomeranz IReddy S(2009)Random test generation with input cube avoidanceIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200194317:1(45-54)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2001943
Pomeranz IReddy S(2009)Dynamic test compaction for a random test generation procedure with input cube avoidance2009 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2009.4796557(672-677)Online publication date: Jan-2009
https://doi.org/10.1109/ASPDAC.2009.4796557
Wang LStroud CCheng K(2009)Logic TestingWiley Encyclopedia of Computer Science and Engineering10.1002/9780470050118.ecse047(1770-1782)Online publication date: 16-Mar-2009
https://doi.org/10.1002/9780470050118.ecse047
Pomeranz IReddy S(2008)Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside TestsProceedings of the 26th IEEE VLSI Test Symposium10.1109/VTS.2008.11(317-322)Online publication date: 27-Apr-2008
https://dl.acm.org/doi/10.1109/VTS.2008.11
Pomeranz IReddy SLauwereins RMadsen J(2007)On test generation by input cube avoidanceProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266478(522-527)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266478
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