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FPGA programming for the masses

Authors:

David F. Bacon,

Rodric Rabbah,

Sunil ShuklaAuthors Info & Claims

Communications of the ACM, Volume 56, Issue 4

Pages 56 - 63

https://doi.org/10.1145/2436256.2436271

Published: 01 April 2013 Publication History

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Abstract

The programmability of FPGAs must improve if they are to be part of mainstream computing.

References

[1]

Auerbach, J., Bacon, D.F., Burcea, I., Cheng, P., Fink, S.J., Rabbah, R. and Shukla, S. A compiler and runtime for heterogeneous computing. In Proceedings of the 49^th ACM/EDAC/IEEE Design Automation Conference (2012), 271--276.

Digital Library

Google Scholar

[2]

Auerbach, J., Bacon, D. F., Cheng, P. and Rabbah, R. Lime: A Java-compatible and synthesizable language for heterogeneous architectures. In Proceedings of the ACM International Conference on Object-oriented Programming Systems Languages and Applications (2010), 89--108.

Digital Library

Google Scholar

[3]

Aydonat, U., Denisenko, D., Freeman, J., Kinsner, M., Neto, D., Wong, J., Yiannacouras, P. and Singh, D.P. From OpenCL to high-performance hardware on FPGAs. In Proceedings of the 22^nd International Conference on Field Programmable Logic and Applications (2012), 531--534.

Google Scholar

[4]

Bachrach, J., Richards, B., Vo, H., Lee, Y., Waterman, A., Avidienis, R., Wawrzynek, J. and Asanovic, K. Chisel: Constructing hardware in a scala-embedded language. In Proceedings of the 49^th ACM/EDAC/IEEE Design Automation Conference (2012), 1212--1221.

Digital Library

Google Scholar

[5]

Berkeley Design Technology. An independent evaluation of the AutoESL AutoPilot high-level synthesis tool. Technical Report, 2010.

Google Scholar

[6]

Brodtkorb, A.R., Dyken, C., Hagen, T.R., Hjelmervik, J.M. and storaasli, O.O. state-of-the-art in heterogeneous computing. Scientific Programming 18, 1 (2010).

Digital Library

Google Scholar

[7]

Cardoso, J. and Diniz, P. Compilation Techniques for Reconfigurable Architectures. Springer, 2009.

Digital Library

Google Scholar

[8]

Coussy, P. and Morawiec, A. High-level Synthesis: From Algorithm to Digital Circuit. Springer, 2008.

Digital Library

Google Scholar

[9]

Dase, C., Falcon, J. S. and MacCleery, B. Motorcycle control prototyping using an FPGA-based embedded control system. IEEE Control Systems 26, 5 (2006), 17--21.

Google Scholar

[10]

Dubach, C., Cheng, P., Rabbah, R., Bacon, D.F., Fink, S.J. Compiling a high-level language for GPUs: (via language support for architectures and compilers). In 33^rd SIGPLAN Symposium for Programming Design and Implementation (2012), 1--12.

Digital Library

Google Scholar

[11]

Edwards, S.A. High-Level Synthesis from the Synchronous Language Esterel. In IEEE/ACM International Workshop on Logic & Synthesis (2002), 401--406.

Google Scholar

[12]

Greaves, D. and Singh, S. Designing application-specific circuits with concurrent C# programs. In Proceedings of the 8^th ACM/IEEE International Conference on Formal Methods and Models for Codesign (2010).

Digital Library

Google Scholar

[13]

Jaaskelainen, P.O., de La Lama, C.S., Huerta, P., Takala, J.H. OpenCL-based design methodology for application-specific processors. Embedded Computer Systems (2010), 223--230.

Google Scholar

[14]

Nikhil, R.S. Abstraction in hardware system design. ACM Queue 9, 8 (2011); http://queue.acm.org/detail.cfm?id=2020861.

Digital Library

Google Scholar

[15]

Owaida, M., Bellas, N., Daloukas, K. and Antonopoulos, C. Synthesis of platform architectures from OpenCL programs. In Field-programmable Custom Computing Machines (2012), 186--193.

Digital Library

Google Scholar

[16]

Papakonstantinou, A., Karthik, G., Stratton, J. A., Chen, D., Cong, J. and Hwu, W.-M.W. 2009. FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs. In Application Specific Processors (2009), 35--42.

Google Scholar

[17]

Sharma, S. and Chen, W. Using Model-based design to accelerate FPGA development for automotive applications. The MathWorks, 2009.

Crossref

Google Scholar

[18]

Sirowy, S. and Forin, A. Where's the beef? Why FPGAs are so fast. Microsoft Research Technical Report MSR-TR-2008-130, 2008.

Google Scholar

[19]

Thomas, D.B., Howes, L., Luk, W. A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation. In ACM/SIGDA International Symposium on Field programmable Gate Arrays (2009), 22--24.

Digital Library

Google Scholar

[20]

WinterGreen Research Inc. Programmable logic IC market shares and forecasts, worldwide, 2010 to 2016. Technical report, 2010.

Google Scholar

[21]

Wulf, W.A. and McKee, S.A. Hitting the memory wall: Implications of the obvious. SIGARCH Computer Architecture News 23, 1 (1995), 20--24.

Digital Library

Google Scholar

[22]

Xilinx. Command line tools user guide. Technical Report UG628 (14.3), 2012.

Google Scholar

[23]

Xilinx. 7 series FPGAs overview. Technical Report DS180 (1.13), 2012.

Google Scholar

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Ciccozzi F(2024)Towards accessible software engineering for heterogeneous hardware2024 International Conference on Artificial Intelligence, Computer, Data Sciences and Applications (ACDSA)10.1109/ACDSA59508.2024.10467878(1-6)Online publication date: 1-Feb-2024
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FPGA programming for the masses
1. Hardware

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Published In

Communications of the ACM Volume 56, Issue 4

April 2013

90 pages

ISSN:0001-0782

EISSN:1557-7317

DOI:10.1145/2436256

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 April 2013

Published in CACM Volume 56, Issue 4

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Matinizadeh SDas A(2024)An Open-Source And Extensible Framework for Fast Prototyping and Benchmarking of Spiking Neural Network Hardware2024 34th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL64840.2024.00042(250-256)Online publication date: 2-Sep-2024
https://doi.org/10.1109/FPL64840.2024.00042
Ciccozzi F(2024)Towards accessible software engineering for heterogeneous hardware2024 International Conference on Artificial Intelligence, Computer, Data Sciences and Applications (ACDSA)10.1109/ACDSA59508.2024.10467878(1-6)Online publication date: 1-Feb-2024
https://doi.org/10.1109/ACDSA59508.2024.10467878
Birath BErnstsson ATinnerholm JKessler C(2024)High-Level Programming of FPGA-Accelerated Systems with Parallel PatternsInternational Journal of Parallel Programming10.1007/s10766-024-00770-352:4(253-273)Online publication date: 1-Aug-2024
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Koraei MCebrian JJahre M(2023)Near-optimal multi-accelerator architectures for predictive maintenance at the edgeFuture Generation Computer Systems10.1016/j.future.2022.10.030140:C(331-343)Online publication date: 8-Feb-2023
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Schlaak CJuang TDubach CGrosser TLee K(2022)Optimizing data reshaping operations in functional IRs for high-level synthesisProceedings of the 23rd ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3519941.3535069(61-72)Online publication date: 14-Jun-2022
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