research-article

Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes

Authors:

David WestwickAuthors Info & Claims

ISPD '13: Proceedings of the 2013 ACM International symposium on Physical Design

Pages 154 - 161

https://doi.org/10.1145/2451916.2451956

Published: 24 March 2013 Publication History

Abstract

Minimizing power and skew for clock networks are critical and difficult tasks which can be greatly affected by buffer sizing. However, buffer sizing is a non-linear problem and most existing algorithms are heuristics that fail to obtain a global minimum. In addition, existing buffer sizing solutions do not usually consider manufacturing variations. Any design made without considering variation can fail to meet design constraints after manufacturing. In this paper, first we proposed an efficient optimization scheme based on geometric programming (GP) for buffer sizing of clock networks. Then, we extended the GP formulation to consider process variations in the buffer sizes using robust optimization (RO). The resultant variation-aware network is examined with SPICE and shown to be superior in terms of robustness to variations while decreasing area, power and average skew.

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Cited By

Han KKahng ALi J(2020)Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock DistributionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288975639:2(478-491)Online publication date: Feb-2020
https://doi.org/10.1109/TCAD.2018.2889756
Uysal NLiu WEwetz RShibuya T(2019)Latency constraint guided buffer sizing and layer assignment for clock trees with useful skewProceedings of the 24th Asia and South Pacific Design Automation Conference10.1145/3287624.3287681(761-766)Online publication date: 21-Jan-2019
https://dl.acm.org/doi/10.1145/3287624.3287681
Chou CHsiao YChang S(2019)Clock Skew Optimization for Voltage Variation2019 China Semiconductor Technology International Conference (CSTIC)10.1109/CSTIC.2019.8755674(1-3)Online publication date: Mar-2019
https://doi.org/10.1109/CSTIC.2019.8755674
Show More Cited By

Index Terms

Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Modeling methodologies

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Published In

cover image ACM Conferences

ISPD '13: Proceedings of the 2013 ACM International symposium on Physical Design

March 2013

194 pages

ISBN:9781450319546

DOI:10.1145/2451916

General Chair:
Cheng-Kok Koh
Purdue University
,
Program Chair:
Cliff Sze
IBM Research

Copyright © 2013 ACM.

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New York, NY, United States

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Published: 24 March 2013

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ISPD'13: International Symposium on Physical Design

March 24 - 27, 2013

Nevada, Stateline, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

Han KKahng ALi J(2020)Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock DistributionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288975639:2(478-491)Online publication date: Feb-2020
https://doi.org/10.1109/TCAD.2018.2889756
Uysal NLiu WEwetz RShibuya T(2019)Latency constraint guided buffer sizing and layer assignment for clock trees with useful skewProceedings of the 24th Asia and South Pacific Design Automation Conference10.1145/3287624.3287681(761-766)Online publication date: 21-Jan-2019
https://dl.acm.org/doi/10.1145/3287624.3287681
Chou CHsiao YChang S(2019)Clock Skew Optimization for Voltage Variation2019 China Semiconductor Technology International Conference (CSTIC)10.1109/CSTIC.2019.8755674(1-3)Online publication date: Mar-2019
https://doi.org/10.1109/CSTIC.2019.8755674
Kim JKim T(2017)Boundary optimization of buffered clock trees for low powerIntegration, the VLSI Journal10.1016/j.vlsi.2016.10.00456:C(86-95)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.10.004
Guthaus M(2016)Clock Design and SynthesisElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-13(261-282)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-13
Farshidi ARakai LBehjat LWestwick D(2016)Variation-aware clock network buffer sizing using robust multi-objective optimizationOptimization and Engineering10.1007/s11081-016-9317-217:2(473-500)Online publication date: 1-Apr-2016
https://doi.org/10.1007/s11081-016-9317-2
Deng CCai YZhou Q(2015)Fast synthesis of low power clock trees based on register clusteringSixteenth International Symposium on Quality Electronic Design10.1109/ISQED.2015.7085444(303-309)Online publication date: Mar-2015
https://doi.org/10.1109/ISQED.2015.7085444
Deng CCai YZhou QChen Z(2015)An efficient buffer sizing algorithm for clock trees considering process variations2015 6th Asia Symposium on Quality Electronic Design (ASQED)10.1109/ACQED.2015.7274017(108-113)Online publication date: Aug-2015
https://doi.org/10.1109/ACQED.2015.7274017
Deng CCai YZhou Q(2015)Register Clustering Methodology for Low Power Clock Tree SynthesisJournal of Computer Science and Technology10.1007/s11390-015-1531-430:2(391-403)Online publication date: 13-Mar-2015
https://doi.org/10.1007/s11390-015-1531-4
Rakai LFarshidi AWestwick DBehjat L(2014)Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing ProblemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.229306733:4(532-545)Online publication date: Apr-2014
https://doi.org/10.1109/TCAD.2013.2293067
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