research-article

Bit mapping for balanced PCM cell programming

Authors:

Bruce R. Childers,

Rami MelhemAuthors Info & Claims

ISCA '13: Proceedings of the 40th Annual International Symposium on Computer Architecture

Pages 428 - 439

https://doi.org/10.1145/2485922.2485959

Published: 23 June 2013 Publication History

Abstract

Write bandwidth is an inherent performance bottleneck for Phase Change Memory (PCM) for two reasons. First, PCM cells have long programming time, and second, only a limited number of PCM cells can be programmed concurrently due to programming current and write circuit constraints,

For each PCM write, the data bits of the write request are typically mapped to multiple cell groups and processed in parallel. We observed that an unbalanced distribution of modified data bits among cell groups significantly increases PCM write time and hurts effective write bandwidth. To address this issue, we first uncover the cyclical and cluster patterns for modified data bits. Next, we propose double XOR mapping (D-XOR) to distribute modified data bits among cell groups in a balanced way. D-XOR can reduce PCM write service time by 45% on average, which increases PCM write throughput by 1.8x. As error correction (redundant bits) is critical for PCM, we also consider the impact of redundancy information in mapping data and error correction bits to cell groups. Our techniques lead to a 51% average reduction in write service time for a PCM main memory with ECC, which increases IPC by 12%.

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Cited By

Oliveira GGhose SGómez-Luna JBoroumand ASavery ARao SQazi SGrignou GThakur RShiu EMutlu O(2023)Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSDIEEE Access10.1109/ACCESS.2023.331788411(105843-105871)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3317884
Narayan AThonnart YVivet PCoskun AJoshi A(2022)Architecting Optically Controlled Phase Change MemoryACM Transactions on Architecture and Code Optimization10.1145/353325219:4(1-26)Online publication date: 7-Dec-2022
https://dl.acm.org/doi/10.1145/3533252
Imran MKwon TYang J(2022)ADAPT: A Write Disturbance-Aware Programming Technique for Scaled Phase Change MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.306870441:4(950-963)Online publication date: Apr-2022
https://doi.org/10.1109/TCAD.2021.3068704
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Index Terms

Bit mapping for balanced PCM cell programming
1. General and reference
  1. Cross-computing tools and techniques
    1. Design
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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cover image ACM Other conferences

ISCA '13: Proceedings of the 40th Annual International Symposium on Computer Architecture

June 2013

686 pages

ISBN:9781450320795

DOI:10.1145/2485922

General Chair:
Avi Mendelson
Technion

ACM SIGARCH Computer Architecture News Volume 41, Issue 3
ICSA '13
June 2013
666 pages
ISSN:0163-5964
DOI:10.1145/2508148
Issue’s Table of Contents

Copyright © 2013 ACM.

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Published: 23 June 2013

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ISCA'13: The 40th Annual International Symposium on Computer Architecture

June 23 - 27, 2013

Tel-Aviv, Israel

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ISCA '13 Paper Acceptance Rate 56 of 288 submissions, 19%;

Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Cited By

Oliveira GGhose SGómez-Luna JBoroumand ASavery ARao SQazi SGrignou GThakur RShiu EMutlu O(2023)Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSDIEEE Access10.1109/ACCESS.2023.331788411(105843-105871)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3317884
Narayan AThonnart YVivet PCoskun AJoshi A(2022)Architecting Optically Controlled Phase Change MemoryACM Transactions on Architecture and Code Optimization10.1145/353325219:4(1-26)Online publication date: 7-Dec-2022
https://dl.acm.org/doi/10.1145/3533252
Imran MKwon TYang J(2022)ADAPT: A Write Disturbance-Aware Programming Technique for Scaled Phase Change MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.306870441:4(950-963)Online publication date: Apr-2022
https://doi.org/10.1109/TCAD.2021.3068704
Imran MKwon TTouba NYang J(2022)CEnT: An Efficient Architecture to Eliminate Intra-Array Write Disturbance in PCMIEEE Transactions on Computers10.1109/TC.2021.306857771:5(992-1007)Online publication date: 1-May-2022
https://doi.org/10.1109/TC.2021.3068577
Zhang CAbdelaal KChen AZhao XWen WGuo XXie Y(2020)ECC cacheProceedings of the 39th International Conference on Computer-Aided Design10.1145/3400302.3415650(1-9)Online publication date: 2-Nov-2020
https://dl.acm.org/doi/10.1145/3400302.3415650
Lee HKim MKim HKim HLee H(2019)Integration and Boost of a Read-Modify-Write Module in Phase Change Memory SystemIEEE Transactions on Computers10.1109/TC.2019.293382668:12(1772-1784)Online publication date: 1-Dec-2019
https://doi.org/10.1109/TC.2019.2933826
Mativenga RHamandawana PKwon SChung T(2019)ExTENDS: Efficient Data Placement and Management for Next Generation PCM-Based Storage SystemsIEEE Access10.1109/ACCESS.2019.29407657(148718-148730)Online publication date: 2019
https://doi.org/10.1109/ACCESS.2019.2940765
Xu JFeng DHua YTong WLiu JLi CLi Z(2018)An efficient PCM-based main memory system via exploiting fine-grained dirtiness of cachelines2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2018.8342273(1616-1621)Online publication date: Mar-2018
https://doi.org/10.23919/DATE.2018.8342273
Rashidi SJalili MSarbazi-Azad H(2018)Improving MLC PCM Performance through Relaxed Write and Read for Intermediate Resistance LevelsACM Transactions on Architecture and Code Optimization10.1145/317796515:1(1-31)Online publication date: 22-Mar-2018
https://dl.acm.org/doi/10.1145/3177965
Han MHan YKim SLee HPark I(2017)Content-Aware Bit Shuffling for Maximizing PCM EnduranceACM Transactions on Design Automation of Electronic Systems10.1145/301744522:3(1-26)Online publication date: 23-May-2017
https://dl.acm.org/doi/10.1145/3017445
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