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Consistent, durable, and safe memory management for byte-addressable non volatile main memory

Authors:

David G. Andersen,

Michael Kaminsky,

Parthasarathy Ranganathan,

Nathan BinkertAuthors Info & Claims

TRIOS '13: Proceedings of the First ACM SIGOPS Conference on Timely Results in Operating Systems

Article No.: 1, Pages 1 - 17

https://doi.org/10.1145/2524211.2524216

Published: 03 November 2013 Publication History

Abstract

This paper presents three building blocks for enabling the efficient and safe design of persistent data stores for emerging non-volatile memory technologies. Taking the fullest advantage of the low latency and high bandwidths of emerging memories such as phase change memory (PCM), spin torque, and memristor necessitates a serious look at placing these persistent storage technologies on the main memory bus. Doing so, however, introduces critical challenges of not sacrificing the data reliability and consistency that users demand from storage. This paper introduces techniques for (1) robust wear-aware memory allocation, (2) preventing of erroneous writes, and (3) consistency-preserving updates that are cache-efficient. We show through our evaluation that these techniques are efficiently implementable and effective by demonstrating a B+-tree implementation modified to make full use of our toolkit.

References

[1]

S. Ahn, Y. Song, C. Jeong, J. Shin, Y. Fai, Y. Hwang, S. Lee, K. Ryoo, S. Lee, J. Park, H. Horii, Y. Ha, J. Yi, B. Kuh, G. Koh, G. Jeong, H. Jeong, K. Kim, and B. Ryu. Highly manufacturable high density phase change memory of 64Mb and beyond. In Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International, pages 907--910, Dec. 2004.

[2]

C. S. Ananian, K. Asanovic, B. C. Kuszmaul, C. E. Leiserson, and S. Lie. Unbounded transactional memory. IEEE Micro, 26: 59--69, Jan. 2006.

Digital Library

[3]

F. Bedeschi, C. Resta, O. Khouri, E. Buda, L. Costa, M. Ferraro, F. Pellizzer, F. Ottogalli, A. Pirovano, M. Tosi, R. Bez, R. Gastaldi, and G. Casagrande. An 8Mb demonstrator for high-density 1.8V phase change memories. In VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on, pages 442--445, June 2004.

[4]

E. D. Berger, K. S. McKinley, R. D. Blumofe, and P. R. Wilson. Hoard: A scalable memory allocator for multithreaded applications. In ASPLOS, pages 117--128, 2000.

Digital Library

[5]

T. Bingmann. Stx b+ tree c++ template classes. http://idlebox.net/2007/stx-btree/, 2008.

[6]

H.-J. Boehm. The Boehm-Demers-Weiser conservative garbage collector. http://www.research.ibm.com/ismm04/slides/boehm-tutorial.ppt, 2004.

[7]

M. Castro, M. Costa, J.-P. Martin, M. Peinado, P. Akritidis, A. Donnelly, P. Barham, and R. Black. Fast byte-granularity software fault isolation. In Proc. 22nd ACM Symposium on Operating Systems Principles (SOSP), pages 45--58, Oct. 2009.

Digital Library

[8]

P. M. Chen, W. T. Ng, S. Chandra, C. Aycock, G. Rajamani, and D. Lowell. The Rio file cache: Surviving operating system crashes. In Proc. 7th International Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 74--83, Oct. 1996.

Digital Library

[9]

A. T. Clements, M. F. Kaashoek, and N. Zeldovich. Radixvm: scalable address spaces for multithreaded applications. In Proceedings of the 8th ACM European Conference on Computer Systems, EuroSys '13, pages 211--224, 2013.

Digital Library

[10]

J. Coburn, A. M. Caulfield, A. Akel, L. M. Grupp, R. K. Gupta, R. Jhala, and S. Swanson. NV-Heaps: Making persistent objects fast and safe with next-generation, non-volatile memories. In Proc. 16th International Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Mar. 2011.

Digital Library

[11]

J. Condit, E. B. Nightingale, C. Frost, E. Ipek, B. Lee, D. Burger, and D. Coetzee. Better I/O through byte-addressable, persistent memory. In Proc. 22nd ACM Symposium on Operating Systems Principles (SOSP), pages 133--146, Oct. 2009.

Digital Library

[12]

G. Copeland, T. Keller, R. Krishnamurthy, and M. Smith. The case for safe RAM. In Proceedings of the 15th International Conference on Very Large Data Bases, VLDB '89, pages 327--335. Morgan Kaufmann Publishers Inc., 1989.

Digital Library

[13]

G. Dhiman, R. Ayoub, and T. Rosing. PDRAM: A Hybrid PRAM and DRAM Main Memory System. In Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE, pages 664--669, July 2009.

Digital Library

[14]

J. Evans. A Scalable Concurrent malloc(3) Implementation for FreeBSD. BSDCan - The BSD Conference, 2006.

[15]

G. R. Ganger and Y. N. Patt. Soft updates: a solution to the metadata update problem in file systems. ACM Transactions on Computer Systems, 18: 127--153, 2000.

Digital Library

[16]

S. Ghemawat and P. Menage. Tcmalloc: Thread-caching malloc. http://goog-perftools.sourceforge.net/doc/tcmalloc.html.

[17]

B. Holden. Latency comparison between HyperTransport™ and PCI-Express™ in communications systems. http://www.hypertransport.org/docs/wp/Low_Latency_Final.pdf, 2006.

[18]

IBM websphere real time for real time Linux, version 2 information center. http://publib.boulder.ibm.com/infocenter/realtime/v2r0/index.jsp, 2006.

[19]

Intel 64 and IA-32 architectures developer's manual: Vol. 1. http://www.intel.com/content/www/us/en/architecture-and-technology/, 2011.

[20]

M. Kharbutli and Y. Solihin. Counter-based cache replacement and bypassing algorithms. Computers, IEEE Transactions on, 57(4): 433--447, Apr. 2008.

Digital Library

[21]

L. Lamport. Proving the correctness of multiprocess programs. Software Engineering, IEEE Transactions on, SE-3(2): 125--143, Mar. 1977.

Digital Library

[22]

D. Lea. A memory allocator. http://g.oswego.edu/dl/html/malloc.html, 2000.

[23]

D. E. Lowell and P. M. Chen. Free transactions with Rio Vista. In Proceedings of the sixteenth ACM Symposium on Operating Systems Principles, SOSP '97, pages 92--101. ACM, 1997.

Digital Library

[24]

C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. Janapa, and R. K. Hazelwood. Pin: Building customized program analysis tools with dynamic instrumentation. In In Programming Language Design and Implementation, pages 190--200. ACM Press, 2005.

Digital Library

[25]

A distributed memory object caching system. http://memcached.org/, 2011.

[26]

K. E. Moore, J. Bobba, M. J. Moravan, M. D. Hill, and D. A. Wood. LogTM: log-based transactional memory. In High-Performance Computer Architecture, 2006. The Twelfth International Symposium on, pages 254--265, Feb. 2006.

[27]

D. Narayanan and O. Hodson. Whole-system persistence. In Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS '12, pages 401--410. ACM, 2012.

Digital Library

[28]

Numonyx. Phase change memory (PCM): A new memory technology to enable new memory usage models. http://www.numonyx.com/Documents/WhitePapers/Numonyx_PhaseChangeMemory_WhitePaper.pdf, 2009.

[29]

Numonyx. Phase change memory. http://www.pdl.cmu.edu/SDI/2009/slides/Numonyx.pdf, 2009.

[30]

M. K. Qureshi, J. Karidis, M. Franceschini, V. Srinivasan, L. Lastras, and B. Abali. Enhancing lifetime and security of pcm-based main memory with start-gap wear leveling. In Proc. ACM MICRO, 2009.

Digital Library

[31]

M. K. Qureshi, A. Seznec, L. Lastras, and M. Franceschini. Practical and secure pcm systems by online detection of malicious write streams. In Proc. HPCA, 2011.

Digital Library

[32]

B. Saha, A.-R. Adl-Tabatabai, and Q. Jacobson. Architectural support for software transactional memory. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 39, pages 185--196. IEEE Computer Society, 2006.

Digital Library

[33]

Virtualized SAP performance with VMware vSphere 4. http://www.vmware.com/files/pdf/perf_vsphere_sap.pdf, 2009.

[34]

M. Satyanarayanan, H. H. Mashburn, P. Kumar, D. C. Steere, and J. J. Kistler. Lightweight recoverable virtual memory. ACM Transactions on Computer Systems, 12: 33--57, Feb. 1994.

Digital Library

[35]

K. Serebryany, D. Bruening, A. Potapenko, and D. Vyukov. Addresssanitizer: a fast address sanity checker. In Proceedings of the 2012 USENIX conference on Annual Technical Conference, USENIX ATC'12, 2012.

Digital Library

[36]

A. Seznec. A phase change memory as a secure main memory. IEEE Comp. Arch. Letters, 9: 5--8, 2010.

Digital Library

[37]

L. Soares and M. Stumm. FlexSC: Flexible system call scheduling with exception-less system calls. In Proc. 9th USENIX OSDI, Oct. 2010.

Digital Library

[38]

M. Sullivan and M. Stonebraker. Using write protected data structures to improve software fault tolerance in highly available database management systems. In Proc. VLDB, 1991.

Digital Library

[39]

M. M. Swift, B. N. Bershad, and H. M. Levy. Improving the reliability of commodity operating systems. ACM Transactions on Computer Systems, pages 77--100, 2005.

Digital Library

[40]

How long does it take to make a context switch? http://blog.tsunanet.net/2010/11/how-long-does-it-take-to-make-context.html.

[41]

S. Venkataraman, N. Tolia, P. Ranganathan, and R. Campbell. Consistent and durable data structures for non-volatile byte-addressable memory. In Proceedings of the 9th USENIX Conference on File and Storage Technologies (FAST '11), Feb. 2011.

Digital Library

[42]

VMware best practices for SAP installations. http://communities.vmware.com/blogs/SAPsolutions/2008/01/18/vmware-best-practices-for-sap-installations, 2008.

[43]

H. Volos, A. J. Tack, and M. M. Swift. Mnemosyne: Lightweight persistent memory. In Proc. 16th International Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Mar. 2011.

Digital Library

[44]

P. R. Wilson. Pointer swizzling at page fault time: Efficiently supporting huge address spaces on standard hardware. SIGARCH Computer Architecture News, 19: 6--13, July 1991.

Digital Library

[45]

P. R. Wilson, M. S. Johnstone, M. Neely, and D. Boles. Dynamic storage allocation: A survey and critical review. In H. G. Baker, editor, IWMM, volume 986 of Lecture Notes in Computer Science, pages 1--116. Springer, 1995.

Digital Library

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Consistent, durable, and safe memory management for byte-addressable non volatile main memory

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cover image ACM Conferences

TRIOS '13: Proceedings of the First ACM SIGOPS Conference on Timely Results in Operating Systems

November 2013

155 pages

ISBN:9781450324632

DOI:10.1145/2524211

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 03 November 2013

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Intel via the Intel Science and Technology Center for Cloud Computing (ISTC-CC)
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SOSP '13: ACM SIGOPS 24th Symposium on Operating Systems Principles

November 3 - 6, 2013

Pennsylvania, Farmington

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https://doi.org/10.1631/FITEE.2200468
Gonçalves JMatos MRodrigues RFedorova ANarayanan DDi Luna GQuerzoni L(2023)Mumak: Efficient and Black-Box Bug Detection for Persistent MemoryProceedings of the Eighteenth European Conference on Computer Systems10.1145/3552326.3587447(734-750)Online publication date: 8-May-2023
https://dl.acm.org/doi/10.1145/3552326.3587447
Wu JLi WWu LYuan MXue CXue JLi Q(2023)Effective Stack Wear Leveling for NVMIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.324087342:10(3250-3263)Online publication date: Oct-2023
https://doi.org/10.1109/TCAD.2023.3240873
Zhang BGong HDu D(2023)PMDB: A Range-Based Key-Value Store on Hybrid NVM-Storage SystemsIEEE Transactions on Computers10.1109/TC.2022.320275572:5(1274-1285)Online publication date: 1-May-2023
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Feng XChen XZhuge QLiu DSha EXue C(2023)V-WAFA: An Endurance Variation Aware Fine-Grained Allocator for Persistent MemoryIEEE Transactions on Computers10.1109/TC.2022.319708672:4(998-1010)Online publication date: 1-Apr-2023
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