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The Transmogrifier-2: a 1 million gate rapid prototyping system

Published: 09 February 1997 Publication History
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    This paper describes the Transmogrifier-2, a second generation multi-FPGA system. The largest version of the system will comprise 16 boards that each contain two Altera 10K50 FPGAs, four I-cube interconnect chips, and up to 8 Mbytes of memory. The inter-FPGA routing architecture of the TM-2 uses a novel interconnect structure, a non-uniform partial crossbar, that provides a constant delay between any two FPGAs in the system. The TM-2 architecture is modular and scalable, meaning that various sized systems can be constructed from the same board, while maintaining routability and the constant delay feature. Other features include a system-level programmable clock that allows single-cycle access to off-chip memory, and programmable clock waveforms with resolution to 10ns. The first Transmogrifier-2 boards have been manufactured and are functional. They have recently been used successfully in some simple graphics acceleration applications.

    References

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    Cited By

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    • (2006)An optimized design flow for fast FPGA-based rapid prototypingField-Programmable Logic and Applications From FPGAs to Computing Paradigm10.1007/BFb0055235(79-88)Online publication date: 27-May-2006
    • (2003)Multiterminal net routing for partial crossbar-based multi-FPGA systemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2002.80052311:1(71-78)Online publication date: 1-Feb-2003
    • (2002)How Fast Is Rapid FPGA-based Prototyping: Lessons and Challenges from the Digital TV Design Prototyping ProjectField-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream10.1007/3-540-46117-5_5(26-35)Online publication date: 16-Aug-2002
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    cover image ACM Conferences
    FPGA '97: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
    February 1997
    174 pages
    ISBN:0897918010
    DOI:10.1145/258305
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 09 February 1997

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    Cited By

    View all
    • (2006)An optimized design flow for fast FPGA-based rapid prototypingField-Programmable Logic and Applications From FPGAs to Computing Paradigm10.1007/BFb0055235(79-88)Online publication date: 27-May-2006
    • (2003)Multiterminal net routing for partial crossbar-based multi-FPGA systemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2002.80052311:1(71-78)Online publication date: 1-Feb-2003
    • (2002)How Fast Is Rapid FPGA-based Prototyping: Lessons and Challenges from the Digital TV Design Prototyping ProjectField-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream10.1007/3-540-46117-5_5(26-35)Online publication date: 16-Aug-2002
    • (2002)FPGA-Based Emulation: Industrial and Custom Prototyping SolutionsField-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing10.1007/3-540-44614-1_8(68-77)Online publication date: 12-Apr-2002
    • (2001)A New Placement Method for Direct Mapping into LUT-Based FPGAsField-Programmable Logic and Applications10.1007/3-540-44687-7_4(27-36)Online publication date: 17-Aug-2001
    • (2001)Prototyping Framework for Reconfigurable ProcessorsField-Programmable Logic and Applications10.1007/3-540-44687-7_2(6-16)Online publication date: 17-Aug-2001
    • (2001)PuMA++: From Behavioral Specification to Multi-FPGA-PrototypeField-Programmable Logic and Applications10.1007/3-540-44687-7_14(133-141)Online publication date: 17-Aug-2001
    • (1999)Multi-terminal net routing for partial crossbar-based multi-FPGA systemsProceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays10.1145/296399.296454(176-185)Online publication date: 1-Feb-1999
    • (1999)Trading quality for compile timeProceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays10.1145/296399.296449(157-166)Online publication date: 1-Feb-1999
    • (1999)A case study: logic emulation-pitfalls and solutionsProceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype (Cat. No.PR00246)10.1109/IWRSP.1999.779047(160-163)Online publication date: 1999
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