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Evaluation of high performance multicache parallel texture mapping

Authors:

Alexis Vartanian,

Jean-Luc Béchennec,

Nathalie Drach-TemamAuthors Info & Claims

ICS '98: Proceedings of the 12th international conference on Supercomputing

Pages 289 - 296

https://doi.org/10.1145/277830.277898

Published: 13 July 1998 Publication History

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Rai SChaudhuri M(2016)Exploiting Dynamic Reuse Probability to Manage Shared Last-level Caches in CPU-GPU Heterogeneous ProcessorsProceedings of the 2016 International Conference on Supercomputing10.1145/2925426.2926266(1-14)Online publication date: 1-Jun-2016
https://dl.acm.org/doi/10.1145/2925426.2926266
Gaur JSrinivasan RSubramoney SChaudhuri MFarrens MKozyrakis C(2013)Efficient management of last-level caches in graphics processors for 3D scene rendering workloadsProceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/2540708.2540742(395-407)Online publication date: 7-Dec-2013
https://dl.acm.org/doi/10.1145/2540708.2540742
Shin HLee JKim L(2006)A cost-effective VLSI architecture for anisotropic texture filtering in limited memory bandwidthIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2006.87176114:3(254-267)Online publication date: 1-Mar-2006
https://dl.acm.org/doi/10.1109/TVLSI.2006.871761
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Published In

ICS '98: Proceedings of the 12th international conference on Supercomputing

July 1998

464 pages

ISBN:089791998X

DOI:10.1145/277830

Chairmen:
Greg Egan
Monash Univ.
,
Richard Brent
Oxford Univ.; and Australian National Univ., Canberra, Australia
,
Dennis Gannon
Indiana Univ.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 July 1998

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ICS98: 1998 International Conference on Supercomputing

Melbourne, Australia

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Cited By

View all

Rai SChaudhuri M(2016)Exploiting Dynamic Reuse Probability to Manage Shared Last-level Caches in CPU-GPU Heterogeneous ProcessorsProceedings of the 2016 International Conference on Supercomputing10.1145/2925426.2926266(1-14)Online publication date: 1-Jun-2016
https://dl.acm.org/doi/10.1145/2925426.2926266
Gaur JSrinivasan RSubramoney SChaudhuri MFarrens MKozyrakis C(2013)Efficient management of last-level caches in graphics processors for 3D scene rendering workloadsProceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/2540708.2540742(395-407)Online publication date: 7-Dec-2013
https://dl.acm.org/doi/10.1145/2540708.2540742
Shin HLee JKim L(2006)A cost-effective VLSI architecture for anisotropic texture filtering in limited memory bandwidthIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2006.87176114:3(254-267)Online publication date: 1-Mar-2006
https://dl.acm.org/doi/10.1109/TVLSI.2006.871761
Slingerland NSmith AFurnari MGallopoulos E(2001)Cache performance for multimedia applicationsProceedings of the 15th international conference on Supercomputing10.1145/377792.377833(204-217)Online publication date: 17-Jun-2001
https://dl.acm.org/doi/10.1145/377792.377833
Igehy HEldridge MHanrahan PKaufman AStraßer WMolnar SSchneider B(1999)Parallel texture cachingProceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware10.1145/311534.311583(95-106)Online publication date: 1-Jul-1999
https://dl.acm.org/doi/10.1145/311534.311583
Vartanian ABechennec JDrach-Temam N(1999)The best distribution for a parallel OpenGL 3D engine with texture cachesProceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550)10.1109/HPCA.2000.824368(399-408)Online publication date: 1999
https://doi.org/10.1109/HPCA.2000.824368

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High performance cache replacement using re-reference interval prediction (RRIP)

High performance cache replacement using re-reference interval prediction (RRIP)

Mapping onto three classes of parallel machines: a case study using the cyclic reduction algorithm